1 /* $NetBSD: kv_dpm.h,v 1.3 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __KV_DPM_H__ 26 #define __KV_DPM_H__ 27 28 #define SMU__NUM_SCLK_DPM_STATE 8 29 #define SMU__NUM_MCLK_DPM_LEVELS 4 30 #define SMU__NUM_LCLK_DPM_LEVELS 8 31 #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */ 32 #include "smu7_fusion.h" 33 #include "ppsmc.h" 34 35 #define SUMO_MAX_HARDWARE_POWERLEVELS 5 36 37 #define SUMO_MAX_NUMBER_VOLTAGES 4 38 39 struct sumo_vid_mapping_entry { 40 u16 vid_2bit; 41 u16 vid_7bit; 42 }; 43 44 struct sumo_vid_mapping_table { 45 u32 num_entries; 46 struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES]; 47 }; 48 49 struct sumo_sclk_voltage_mapping_entry { 50 u32 sclk_frequency; 51 u16 vid_2bit; 52 u16 rsv; 53 }; 54 55 struct sumo_sclk_voltage_mapping_table { 56 u32 num_max_dpm_entries; 57 struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS]; 58 }; 59 60 #define TRINITY_AT_DFLT 30 61 62 #define KV_NUM_NBPSTATES 4 63 64 enum kv_pt_config_reg_type { 65 KV_CONFIGREG_MMR = 0, 66 KV_CONFIGREG_SMC_IND, 67 KV_CONFIGREG_DIDT_IND, 68 KV_CONFIGREG_CACHE, 69 KV_CONFIGREG_MAX 70 }; 71 72 struct kv_pt_config_reg { 73 u32 offset; 74 u32 mask; 75 u32 shift; 76 u32 value; 77 enum kv_pt_config_reg_type type; 78 }; 79 80 struct kv_lcac_config_values { 81 u32 block_id; 82 u32 signal_id; 83 u32 t; 84 }; 85 86 struct kv_lcac_config_reg { 87 u32 cntl; 88 u32 block_mask; 89 u32 block_shift; 90 u32 signal_mask; 91 u32 signal_shift; 92 u32 t_mask; 93 u32 t_shift; 94 u32 enable_mask; 95 u32 enable_shift; 96 }; 97 98 struct kv_pl { 99 u32 sclk; 100 u8 vddc_index; 101 u8 ds_divider_index; 102 u8 ss_divider_index; 103 u8 allow_gnb_slow; 104 u8 force_nbp_state; 105 u8 display_wm; 106 u8 vce_wm; 107 }; 108 109 struct kv_ps { 110 struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; 111 u32 num_levels; 112 bool need_dfs_bypass; 113 u8 dpm0_pg_nb_ps_lo; 114 u8 dpm0_pg_nb_ps_hi; 115 u8 dpmx_nb_ps_lo; 116 u8 dpmx_nb_ps_hi; 117 }; 118 119 struct kv_sys_info { 120 u32 bootup_uma_clk; 121 u32 bootup_sclk; 122 u32 dentist_vco_freq; 123 u32 nb_dpm_enable; 124 u32 nbp_memory_clock[KV_NUM_NBPSTATES]; 125 u32 nbp_n_clock[KV_NUM_NBPSTATES]; 126 u16 bootup_nb_voltage_index; 127 u8 htc_tmp_lmt; 128 u8 htc_hyst_lmt; 129 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; 130 struct sumo_vid_mapping_table vid_mapping_table; 131 u32 uma_channel_number; 132 }; 133 134 struct kv_power_info { 135 u32 at[SUMO_MAX_HARDWARE_POWERLEVELS]; 136 u32 voltage_drop_t; 137 struct kv_sys_info sys_info; 138 struct kv_pl boot_pl; 139 bool enable_nb_ps_policy; 140 bool disable_nb_ps3_in_battery; 141 bool video_start; 142 bool battery_state; 143 u32 lowest_valid; 144 u32 highest_valid; 145 u16 high_voltage_t; 146 bool cac_enabled; 147 bool bapm_enable; 148 /* smc offsets */ 149 u32 sram_end; 150 u32 dpm_table_start; 151 u32 soft_regs_start; 152 /* dpm SMU tables */ 153 u8 graphics_dpm_level_count; 154 u8 uvd_level_count; 155 u8 vce_level_count; 156 u8 acp_level_count; 157 u8 samu_level_count; 158 u16 fps_high_t; 159 SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE]; 160 SMU7_Fusion_ACPILevel acpi_level; 161 SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD]; 162 SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE]; 163 SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP]; 164 SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU]; 165 u8 uvd_boot_level; 166 u8 vce_boot_level; 167 u8 acp_boot_level; 168 u8 samu_boot_level; 169 u8 uvd_interval; 170 u8 vce_interval; 171 u8 acp_interval; 172 u8 samu_interval; 173 u8 graphics_boot_level; 174 u8 graphics_interval; 175 u8 graphics_therm_throttle_enable; 176 u8 graphics_voltage_change_enable; 177 u8 graphics_clk_slow_enable; 178 u8 graphics_clk_slow_divider; 179 u8 fps_low_t; 180 u32 low_sclk_interrupt_t; 181 bool uvd_power_gated; 182 bool vce_power_gated; 183 bool acp_power_gated; 184 bool samu_power_gated; 185 bool nb_dpm_enabled; 186 /* flags */ 187 bool enable_didt; 188 bool enable_dpm; 189 bool enable_auto_thermal_throttling; 190 bool enable_nb_dpm; 191 /* caps */ 192 bool caps_cac; 193 bool caps_power_containment; 194 bool caps_sq_ramping; 195 bool caps_db_ramping; 196 bool caps_td_ramping; 197 bool caps_tcp_ramping; 198 bool caps_sclk_throttle_low_notification; 199 bool caps_fps; 200 bool caps_uvd_dpm; 201 bool caps_uvd_pg; 202 bool caps_vce_pg; 203 bool caps_samu_pg; 204 bool caps_acp_pg; 205 bool caps_stable_p_state; 206 bool caps_enable_dfs_bypass; 207 bool caps_sclk_ds; 208 struct amdgpu_ps current_rps; 209 struct kv_ps current_ps; 210 struct amdgpu_ps requested_rps; 211 struct kv_ps requested_ps; 212 }; 213 214 /* XXX are these ok? */ 215 #define KV_TEMP_RANGE_MIN (90 * 1000) 216 #define KV_TEMP_RANGE_MAX (120 * 1000) 217 218 /* kv_smc.c */ 219 int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id); 220 int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask); 221 int amdgpu_kv_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, 222 PPSMC_Msg msg, u32 parameter); 223 int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 224 u32 *value, u32 limit); 225 int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable); 226 int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable); 227 int amdgpu_kv_copy_bytes_to_smc(struct amdgpu_device *adev, 228 u32 smc_start_address, 229 const u8 *src, u32 byte_count, u32 limit); 230 231 #endif 232
Indexes created Mon Sep 22 13:09:51 GMT 2025