1 /* $NetBSD: adm5120reg.h,v 1.2 2008/04/28 20:23:27 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /*- 34 * Copyright (c) 2001 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Jason R. Thorpe. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 50 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 #ifndef _ADM5120REG_H_ 63 #define _ADM5120REG_H_ 64 65 /* 66 * Memory map and register definitions for the Alchemy Semiconductor Pb1000. 67 */ 68 69 /* Last byte of physical address space. */ 70 #define ADM5120_TOP 0x1fffffff 71 #define ADM5120_BOTTOM 0x0 72 73 /* Flash addresses */ 74 #define ADM5120_BASE_SRAM0 0x1fc00000 75 76 /* UARTs */ 77 #define ADM5120_BASE_UART1 0x12800000 78 #define ADM5120_BASE_UART0 0x12600000 79 80 /* ICU */ 81 #define ADM5120_BASE_ICU 0x12200000 82 #define ICU_STATUS_REG 0x00 83 #define ICU_RAW_STATUS_REG 0x04 84 #define ICU_ENABLE_REG 0x08 85 #define ICU_DISABLE_REG 0x0c 86 #define ICU_SOFT_REG 0x10 87 #define ICU_MODE_REG 0x14 88 #define ICU_FIQ_STATUS_REG 0x18 89 #define ICU_TESTSRC_REG 0x1c 90 #define ICU_SRCSEL_REG 0x20 91 #define ICU_LEVEL_REG 0x24 92 #define ICU_INT_MASK 0x3ff 93 94 /* Switch */ 95 #define ADM5120_BASE_SWITCH 0x12000000 96 #define SW_CODE_REG 0x00 97 #define CLKS_MASK 0x00300000 98 #define CLKS_175MHZ 0x00000000 99 #define CLKS_200MHZ 0x00100000 100 #define SW_SFTRES_REG 0x04 101 #define SW_MEMCONT_REG 0x1c 102 #define SDRAM_SIZE_4MBYTES 0x0001 103 #define SDRAM_SIZE_8MBYTES 0x0002 104 #define SDRAM_SIZE_16MBYTES 0x0003 105 #define SDRAM_SIZE_64MBYTES 0x0004 106 #define SDRAM_SIZE_128MBYTES 0x0005 107 #define SDRAM_SIZE_MASK 0x0007 108 #define SRAM0_SIZE_SHIFT 8 109 #define SRAM1_SIZE_SHIFT 16 110 #define SRAM_MASK 0x0007 111 #define SRAM_SSIZE 0x40000 112 113 #define ADM5120_BASE_PCI_CONFDATA 0x115ffff8 114 #define ADM5120_BASE_PCI_CONFADDR 0x115ffff0 115 #define ADM5120_BASE_PCI_IO 0x11500000 116 #define ADM5120_BASE_PCI_MEM 0x11400000 117 #define ADM5120_BASE_USB 0x11200000 118 #define ADM5120_BASE_MPMC 0x11000000 119 #define ADM5120_BASE_EXTIO1 0x10e00000 120 #define ADM5120_BASE_EXTIO0 0x10c00000 121 #define ADM5120_BASE_RSVD0 0x10800000 122 #define ADM5120_BASE_SRAM1 0x10000000 123 124 #define _REG_READ(b, o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((b) + (o))) 125 #define SW_READ(o) _REG_READ(ADM5120_BASE_SWITCH, o) 126 127 #define _REG_WRITE(b, o, v) (_REG_READ(b, o)) = (v) 128 #define SW_WRITE(o, v) _REG_WRITE(ADM5120_BASE_SWITCH,o, v) 129 130 /* USB */ 131 132 /* Watchdog Timers: base address is switch controller */ 133 134 #define ADM5120_WDOG0 0x00c0 135 #define ADM5120_WDOG1 0x00c4 136 137 #define ADM5120_WDOG0_WTTR __BIT(31) /* 0: do not reset, 138 * 1: reset on wdog expiration 139 */ 140 #define ADM5120_WDOG1_WDE __BIT(31) /* 0: deactivate, 141 * 1: drop all CPU-bound 142 * packets, disable flow 143 * control on all ports. 144 */ 145 #define ADM5120_WDOG_WTS_MASK __BITS(30, 16) /* Watchdog Timer Set: 146 * timer expires when it 147 * reaches WTS. Units of 148 * 10ms. 149 */ 150 #define ADM5120_WDOG_RSVD __BIT(15) 151 #define ADM5120_WDOG_WT_MASK __BITS(14, 0) /* Watchdog Timer: 152 * counts up, write to clear. 153 */ 154 155 /* GPIO: base address is switch controller */ 156 #define ADM5120_GPIO0 0x00b8 157 158 #define ADM5120_GPIO0_OV __BITS(31, 24) /* rw: output value */ 159 #define ADM5120_GPIO0_OE __BITS(23, 16) /* rw: output enable, 160 * bit[n] = 0 -> input 161 * bit[n] = 1 -> output 162 */ 163 #define ADM5120_GPIO0_IV __BITS(15, 8) /* ro: input value */ 164 #define ADM5120_GPIO0_RSVD __BITS(7, 0) /* rw: reserved */ 165 166 #define ADM5120_GPIO2 0x00bc 167 #define ADM5120_GPIO2_EW __BIT(6) /* 1: enable wait state pin, 168 * pin GPIO[0], for GPIO[1] 169 * or GPIO[3] Chip Select: 170 * memory controller waits for 171 * WAIT# inactive (high). 172 */ 173 #define ADM5120_GPIO2_CSX1 __BIT(5) /* 1: GPIO[3:4] act as 174 * Chip Select for 175 * External I/O 1 (CSX1) 176 * and External Interrupt 1 177 * (INTX1), respectively. 178 * 0: CSX1/INTX1 disabled 179 */ 180 #define ADM5120_GPIO2_CSX0 __BIT(4) /* 1: GPIO[1:2] act as 181 * Chip Select for 182 * External I/O 0 (CSX0) 183 * and External Interrupt 0 184 * (INTX0), respectively. 185 * 0: CSX0/INTX0 disabled 186 */ 187 188 /* MultiPort Memory Controller (MPMC) */ 189 190 #define ADM5120_MPMC_CONTROL 0x000 191 #define ADM5120_MPMC_CONTROL_DWB __BIT(3) /* write 1 to 192 * drain write 193 * buffers. write 0 194 * for normal buffer 195 * operation. 196 */ 197 #define ADM5120_MPMC_CONTROL_LPM __BIT(2) /* 1: activate low-power 198 * mode. SDRAM is 199 * still refreshed. 200 */ 201 #define ADM5120_MPMC_CONTROL_AM __BIT(1) /* 1: address mirror: 202 * static memory 203 * chip select 0 204 * is mapped to chip 205 * select 1. 206 */ 207 #define ADM5120_MPMC_CONTROL_ME __BIT(0) /* 0: disable MPMC. 208 * DRAM is not 209 * refreshed. 210 * 1: enable MPMC. 211 */ 212 213 #define ADM5120_MPMC_STATUS 0x004 214 #define ADM5120_MPMC_STATUS_SRA __BIT(2) /* read-only 215 * MPMC operating mode 216 * indication, 217 * 1: self-refresh 218 * acknowledge 219 * 0: normal mode 220 */ 221 #define ADM5120_MPMC_STATUS_WBS __BIT(1) /* read-only 222 * write-buffer status, 223 * 0: buffers empty 224 * 1: contain data 225 */ 226 #define ADM5120_MPMC_STATUS_BU __BIT(0) /* read-only MPMC 227 * "busy" indication, 228 * 0: MPMC idle 229 * 1: MPMC is performing 230 * memory transactions 231 */ 232 233 #define ADM5120_MPMC_SEW 0x080 234 #define ADM5120_MPMC_SEW_RSVD __BITS(31, 10) 235 #define ADM5120_MPMC_SEW_EWTO __BITS(9, 0) /* timeout access after 236 * 16 * (n + 1) clock cycles 237 * (XXX which clock?) 238 */ 239 240 #define ADM5120_MPMC_SC(__i) (0x200 + 0x020 * (__i)) 241 #define ADM5120_MPMC_SC_RSVD0 __BITS(31, 21) 242 #define ADM5120_MPMC_SC_WP __BIT(20) /* 1: write protect */ 243 #define ADM5120_MPMC_SC_BE __BIT(20) /* 1: enable write buffer */ 244 #define ADM5120_MPMC_SC_RSVD1 __BITS(18, 9) 245 #define ADM5120_MPMC_SC_EW __BIT(8) /* 1: enable extended wait; 246 */ 247 #define ADM5120_MPMC_SC_BLS __BIT(7) /* 0: byte line state pins 248 * are active high on read, 249 * active low on write. 250 * 251 * 1: byte line state pins 252 * are active low on read and 253 * on write. 254 */ 255 #define ADM5120_MPMC_SC_CCP __BIT(6) /* 0: chip select is active low, 256 * 1: active high 257 */ 258 #define ADM5120_MPMC_SC_RSVD2 __BITS(5, 4) 259 #define ADM5120_MPMC_SC_PM __BIT(3) /* 0: page mode disabled, 260 * 1: enable asynchronous 261 * page mode four 262 */ 263 #define ADM5120_MPMC_SC_RSVD3 __BIT(2) 264 #define ADM5120_MPMC_SC_MW_MASK __BITS(1, 0) /* memory width, bits */ 265 #define ADM5120_MPMC_SC_MW_8B __SHIFTIN(0, ADM5120_MPMC_SC_MW_MASK) 266 #define ADM5120_MPMC_SC_MW_16B __SHIFTIN(1, ADM5120_MPMC_SC_MW_MASK) 267 #define ADM5120_MPMC_SC_MW_32B __SHIFTIN(2, ADM5120_MPMC_SC_MW_MASK) 268 #define ADM5120_MPMC_SC_MW_RSVD __SHIFTIN(3, ADM5120_MPMC_SC_MW_MASK) 269 270 #define ADM5120_MPMC_SWW(__i) (0x204 + 0x020 * (__i)) 271 #define ADM5120_MPMC_SWW_RSVD __BITS(31, 4) 272 #define ADM5120_MPMC_SWW_WWE __BITS(3, 0) /* delay (n + 1) * HCLK cycles 273 * after asserting chip select 274 * (CS) before asserting write 275 * enable (WE) 276 */ 277 278 #define ADM5120_MPMC_SWO(__i) (0x208 + 0x020 * (__i)) 279 #define ADM5120_MPMC_SWO_RSVD __BITS(31, 4) 280 #define ADM5120_MPMC_SWO_WOE __BITS(3, 0) /* delay n * HCLK cycles 281 * after asserting chip select 282 * before asserting output 283 * enable (OE) 284 */ 285 286 #define ADM5120_MPMC_SWR(__i) (0x20c + 0x020 * (__i)) 287 #define ADM5120_MPMC_SWR_RSVD __BITS(31, 5) 288 #define ADM5120_MPMC_SWR_NMRW __BITS(4, 0) /* read wait states for 289 * either first page-mode 290 * access or for non-page mode 291 * read, (n + 1) * HCLK cycles 292 */ 293 294 #define ADM5120_MPMC_SWP(__i) (0x210 + 0x020 * (__i)) 295 #define ADM5120_MPMC_SWP_RSVD __BITS(31, 5) 296 #define ADM5120_MPMC_SWP_WPS __BITS(4, 0) /* read wait states for 297 * second and subsequent 298 * page-mode read, 299 * (n + 1) * HCLK cycles 300 */ 301 302 #define ADM5120_MPMC_SWWR(__i) (0x214 + 0x020 * (__i)) 303 #define ADM5120_MPMC_SWWR_RSVD __BITS(31, 5) 304 #define ADM5120_MPMC_SWWR_WWS __BITS(4, 0) /* write wait states after 305 * the first read (??), 306 * (n + 2) * HCLK cycles 307 */ 308 309 #define ADM5120_MPMC_SWT(__i) (0x218 + 0x020 * (__i)) 310 #define ADM5120_MPMC_SWT_RSVD __BITS(31, 4) 311 #define ADM5120_MPMC_SWT_WAITTURN __BITS(3, 0) /* bus turnaround time, 312 * (n + 1) * HCLK cycles 313 */ 314 315 #endif /* _ADM5120REG_H_ */ 316
Indexes created Sun Sep 21 15:09:59 GMT 2025