1 /* $NetBSD: tx39sibreg.h,v 1.4 2008/04/28 20:23:22 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Toshiba TX3912 SIB module 33 */ 34 35 #define TX39_SIBSIZE_REG 0x060 /* W */ 36 #define TX39_SIBSNDRXSTART_REG 0x064 /* W */ 37 #define TX39_SIBSNDTXSTART_REG 0x068 /* W */ 38 #define TX39_SIBTELRXSTART_REG 0x06c /* W */ 39 #define TX39_SIBTELTXSTART_REG 0x070 /* W */ 40 #define TX39_SIBCTRL_REG 0x074 /* R/W */ 41 #define TX39_SIBSNDHOLD_REG 0x078 /* R/W */ 42 #define TX39_SIBTELHOLD_REG 0x07c /* R/W */ 43 #define TX39_SIBSF0CTRL_REG 0x080 /* R/W */ 44 #define TX39_SIBSF1CTRL_REG 0x084 /* R/W */ 45 #define TX39_SIBSF0STAT_REG 0x088 /* R */ 46 #define TX39_SIBSF1STAT_REG 0x08c /* R */ 47 #define TX39_SIBDMACTRL_REG 0x090 /* R/W */ 48 49 /* 50 * SIB DMA 51 */ 52 #define TX39_SIBDMA_SIZE 16384 53 54 /* 55 * SIB Size Register 56 */ 57 #define TX39_SIBSIZE_SND_SHIFT 18 58 #define TX39_SIBSIZE_TEL_SHIFT 2 59 #define TX39_SIBSIZE_MASK 0xfff 60 61 #define TX39_SIBSIZE_SNDSIZE_SET(cr, val) \ 62 ((cr) | (((((val) >> 2) - 1) << TX39_SIBSIZE_SND_SHIFT) & \ 63 (TX39_SIBSIZE_MASK << TX39_SIBSIZE_SND_SHIFT))) 64 #define TX39_SIBSIZE_TELSIZE_SET(cr, val) \ 65 ((cr) | (((((val) >> 2) - 1) << TX39_SIBSIZE_TEL_SHIFT) & \ 66 (TX39_SIBSIZE_MASK << TX39_SIBSIZE_TEL_SHIFT))) 67 68 /* 69 * SIB Sound RX Start Register 70 * [1:0] reserved 71 */ 72 /* 73 * SIB Sound TX Start Register 74 * [1:0] reserved 75 */ 76 /* 77 * SIB Telecom RX Start Register 78 * [1:0] reserved 79 */ 80 /* 81 * SIB Telecom TX Start Register 82 * [1:0] reserved 83 */ 84 /* 85 * SIB Control Register 86 */ 87 #define TX39_SIBCTRL_SIBIRQ 0x80000000 88 #define TX39_SIBCTRL_ENCNTTEST 0x40000000 /* Don't set */ 89 #define TX39_SIBCTRL_ENDMATEST 0x20000000 /* Don't set */ 90 #define TX39_SIBCTRL_SNDMONO 0x10000000 91 #define TX39_SIBCTRL_RMONOSNDIN 0x08000000 92 93 #define TX39_SIBCTRL_SCLKDIV_SHIFT 24 94 #define TX39_SIBCTRL_SCLKDIV_MASK 0x7 95 #define TX39_SIBCTRL_SCLKDIV(cr) \ 96 (((cr) >> TX39_SIBCTRL_SCLKDIV_SHIFT) & \ 97 TX39_SIBCTRL_SCLKDIV_MASK) 98 #define TX39_SIBCTRL_SCLKDIV_SET(cr, val) \ 99 ((cr) | (((val) << TX39_SIBCTRL_SCLKDIV_SHIFT) & \ 100 (TX39_SIBCTRL_SCLKDIV_MASK << TX39_SIBCTRL_SCLKDIV_SHIFT))) 101 102 #define TX39_SIBCTRL_TEL16 0x00800000 103 104 #define TX39_SIBCTRL_TELFSDIV_SHIFT 16 105 #define TX39_SIBCTRL_TELFSDIV_MASK 0x7f 106 #define TX39_SIBCTRL_TELFSDIV(cr) \ 107 (((cr) >> TX39_SIBCTRL_TELFSDIV_SHIFT) & \ 108 TX39_SIBCTRL_TELFSDIV_MASK) 109 #define TX39_SIBCTRL_TELFSDIV_SET(cr, val) \ 110 ((cr) | (((val) << TX39_SIBCTRL_TELFSDIV_SHIFT) & \ 111 (TX39_SIBCTRL_TELFSDIV_MASK << TX39_SIBCTRL_TELFSDIV_SHIFT))) 112 113 #define TX39_SIBCTRL_SND16 0x00008000 114 115 #define TX39_SIBCTRL_SNDFSDIV_SHIFT 8 116 #define TX39_SIBCTRL_SNDFSDIV_MASK 0x7f 117 #define TX39_SIBCTRL_SNDFSDIV(cr) \ 118 (((cr) >> TX39_SIBCTRL_SNDFSDIV_SHIFT) & \ 119 TX39_SIBCTRL_SNDFSDIV_MASK) 120 #define TX39_SIBCTRL_SNDFSDIV_SET(cr, val) \ 121 ((cr) | (((val) << TX39_SIBCTRL_SNDFSDIV_SHIFT) & \ 122 (TX39_SIBCTRL_SNDFSDIV_MASK << TX39_SIBCTRL_SNDFSDIV_SHIFT))) 123 124 #define TX39_SIBCTRL_SELTELSF1 0x00000080 125 #define TX39_SIBCTRL_SELSNDSF1 0x00000040 126 #define TX39_SIBCTRL_ENTEL 0x00000020 127 #define TX39_SIBCTRL_ENSND 0x00000010 128 #define TX39_SIBCTRL_SIBLOOP 0x00000008 129 #define TX39_SIBCTRL_ENSF1 0x00000004 130 #define TX39_SIBCTRL_ENSF0 0x00000002 131 #define TX39_SIBCTRL_ENSIB 0x00000001 132 133 /* 134 * SIB Sound RX/TX Holding Register 135 */ 136 /* 137 * SIB Telecom RX/TX Holding Register 138 */ 139 140 /* 141 * SIB Subframe 0 Control Register 142 * SIB Subframe 0 Status Register 143 */ 144 /* Control/Status bit, field definition (See also UCB1200) */ 145 #define TX39_SIBSF0_REGADDR_SHIFT 27 146 #define TX39_SIBSF0_REGADDR_MASK 0xf 147 #define TX39_SIBSF0_REGADDR(cr) \ 148 (((cr) >> TX39_SIBSF0_REGADDR_SHIFT) & \ 149 TX39_SIBSF0_REGADDR_MASK) 150 #define TX39_SIBSF0_REGADDR_SET(cr, val) \ 151 ((cr) | (((val) << TX39_SIBSF0_REGADDR_SHIFT) & \ 152 (TX39_SIBSF0_REGADDR_MASK << TX39_SIBSF0_REGADDR_SHIFT))) 153 154 #define TX39_SIBSF0_WRITE 0x04000000 155 #define TX39_SIBSF0_SNDVALID 0x00020000 156 #define TX39_SIBSF0_TELVALID 0x00010000 157 158 #define TX39_SIBSF0_REGDATA_SHIFT 0 159 #define TX39_SIBSF0_REGDATA_MASK 0xffff 160 #define TX39_SIBSF0_REGDATA(cr) \ 161 (((cr) >> TX39_SIBSF0_REGDATA_SHIFT) & \ 162 TX39_SIBSF0_REGDATA_MASK) 163 #define TX39_SIBSF0_REGDATA_SET(cr, val) \ 164 ((cr) | (((val) << TX39_SIBSF0_REGDATA_SHIFT) & \ 165 (TX39_SIBSF0_REGDATA_MASK << TX39_SIBSF0_REGDATA_SHIFT))) 166 #define TX39_SIBSF0_REGDATA_CLR(cr) \ 167 ((cr) &= ~(TX39_SIBSF0_REGDATA_MASK << TX39_SIBSF0_REGDATA_SHIFT)) 168 169 /* 170 * SIB Subframe 1 Control Register 171 */ 172 #define TX39_SIBSF1CTRL_MUTE 0x04000000 173 #define TX39_SIBSF1CTRL_MUXL 0x02000000 174 #define TX39_SIBSF1CTRL_MUXR 0x01000000 175 176 #define TX39_SIBSF1CTRL_ADCGAINL_SHIFT 20 177 #define TX39_SIBSF1CTRL_ADCGAINL_MASK 0xf 178 #define TX39_SIBSF1CTRL_ADCGAINL_SET(cr, val) \ 179 ((cr) | (((val) << TX39_SIBSF1CTRL_ADCGAINL_SHIFT) & \ 180 (TX39_SIBSF1CTRL_ADCGAINL_MASK << TX39_SIBSF1CTRL_ADCGAINL_SHIFT))) 181 182 #define TX39_SIBSF1CTRL_ADCGAINR_SHIFT 16 183 #define TX39_SIBSF1CTRL_ADCGAINR_MASK 0xf 184 #define TX39_SIBSF1CTRL_ADCGAINR_SET(cr, val) \ 185 ((cr) | (((val) << TX39_SIBSF1CTRL_ADCGAINR_SHIFT) & \ 186 (TX39_SIBSF1CTRL_ADCGAINR_MASK << TX39_SIBSF1CTRL_ADCGAINR_SHIFT))) 187 188 #define TX39_SIBSF1CTRL_DACATTNL_SHIFT 8 189 #define TX39_SIBSF1CTRL_DACATTNL_MASK 0xf 190 #define TX39_SIBSF1CTRL_DACATTNL_SET(cr, val) \ 191 ((cr) | (((val) << TX39_SIBSF1CTRL_DACATTNL_SHIFT) & \ 192 (TX39_SIBSF1CTRL_DACATTNL_MASK << TX39_SIBSF1CTRL_DACATTNL_SHIFT))) 193 194 #define TX39_SIBSF1CTRL_DACATTNR_SHIFT 4 195 #define TX39_SIBSF1CTRL_DACATTNR_MASK 0xf 196 #define TX39_SIBSF1CTRL_DACATTNR_SET(cr, val) \ 197 ((cr) | (((val) << TX39_SIBSF1CTRL_DACATTNR_SHIFT) & \ 198 (TX39_SIBSF1CTRL_DACATTNR_MASK << TX39_SIBSF1CTRL_DACATTNR_SHIFT))) 199 200 #define TX39_SIBSF1CTRL_DIGITALOUT_SHIFT 0 201 #define TX39_SIBSF1CTRL_DIGITALOUT_MASK 0xf 202 #define TX39_SIBSF1CTRL_DIGITALOUT_SET(cr, val) \ 203 ((cr) | (((val) << TX39_SIBSF1CTRL_DIGITALOUT_SHIFT) & \ 204 (TX39_SIBSF1CTRL_DIGITALOUT_MASK << TX39_SIBSF1CTRL_DIGITALOUT_SHIFT))) 205 206 /* 207 * SIB Subframe 1 Status Register 208 */ 209 #define TX39_SIBSF1STAT_ADCVALID 0x04000000 210 #define TX39_SIBSF1STAT_ADCCLIPL 0x02000000 211 #define TX39_SIBSF1STAT_ADCCLIPR 0x01000000 212 213 #define TX39_SIBSF1STAT_ERROR_SHIFT 20 214 #define TX39_SIBSF1STAT_ERROR_MASK 0xf 215 #define TX39_SIBSF1STAT_ERROR_SET(cr, val) \ 216 ((cr) | (((val) << TX39_SIBSF1STAT_ERROR_SHIFT) & \ 217 (TX39_SIBSF1STAT_ERROR_MASK << TX39_SIBSF1STAT_ERROR_SHIFT))) 218 219 #define TX39_SIBSF1STAT_REVISION_SHIFT 16 220 #define TX39_SIBSF1STAT_REVISION_MASK 0xf 221 #define TX39_SIBSF1STAT_REVISION_SET(cr, val) \ 222 ((cr) | (((val) << TX39_SIBSF1STAT_REVISION_SHIFT) & \ 223 (TX39_SIBSF1STAT_REVISION_MASK << TX39_SIBSF1STAT_REVISION_SHIFT))) 224 225 #define TX39_SIBSF1STAT_DIGITALIN_SHIFT 0 226 #define TX39_SIBSF1STAT_DIGITALIN_MASK 0xf 227 #define TX39_SIBSF1STAT_DIGITALIN_SET(cr, val) \ 228 ((cr) | (((val) << TX39_SIBSF1STAT_DIGITALIN_SHIFT) & \ 229 (TX39_SIBSF1STAT_DIGITALIN_MASK << TX39_SIBSF1STAT_DIGITALIN_SHIFT))) 230 231 /* 232 * SIB DMA Control Register 233 */ 234 #define TX39_SIBDMACTRL_SNDBUFF1TIME 0x80000000 235 #define TX39_SIBDMACTRL_SNDDMALOOP 0x40000000 236 237 #define TX39_SIBDMACTRL_SNDDMAPTR_SHIFT 18 238 #define TX39_SIBDMACTRL_SNDDMAPTR_MASK 0xfff 239 #define TX39_SIBDMACTRL_SNDDMAPTR(cr) \ 240 (((cr) >> TX39_SIBDMACTRL_SNDDMAPTR_SHIFT) & \ 241 TX39_SIBDMACTRL_SNDDMAPTR_MASK) 242 243 #define TX39_SIBDMACTRL_ENDMARXSND 0x00020000 244 #define TX39_SIBDMACTRL_ENDMATXSND 0x00010000 245 #define TX39_SIBDMACTRL_TELBUFF1TIME 0x00008000 246 #define TX39_SIBDMACTRL_TELDMALOOP 0x00004000 247 248 #define TX39_SIBDMACTRL_TELDMAPTR_SHIFT 2 249 #define TX39_SIBDMACTRL_TELDMAPTR_MASK 0xfff 250 #define TX39_SIBDMACTRL_TELDMAPTR(cr) \ 251 (((cr) >> TX39_SIBDMACTRL_TELDMAPTR_SHIFT) & \ 252 TX39_SIBDMACTRL_TELDMAPTR_MASK) 253 254 #define TX39_SIBDMACTRL_ENDMARXTEL 0x00000002 255 #define TX39_SIBDMACTRL_ENDMATXTEL 0x00000001 256 257
Indexes created Fri Sep 26 08:10:20 GMT 2025