1 /* $NetBSD: tx39spireg.h,v 1.3 2008/04/28 20:23:22 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Toshiba TX3912/3922 SPI module 33 */ 34 35 #define TX39_SPICTRL_REG 0x160 36 #define TX39_SPITXHOLD_REG 0x164 /* W */ 37 #define TX39_SPIRXHOLD_REG 0x164 /* R */ 38 39 /* 40 * SPI Control Register 41 */ 42 /* R */ 43 #define TX39_SPICTRL_SPION 0x00020000 44 #define TX39_SPICTRL_EMPTY 0x00010000 45 /* R/W */ 46 #define TX39_SPICTRL_DELAYVAL_SHIFT 12 47 #define TX39_SPICTRL_DELAYVAL_MASK 0xf 48 #define TX39_SPICTRL_DELAYVAL(cr) \ 49 (((cr) >> TX39_SPICTRL_DELAYVAL_SHIFT) & \ 50 TX39_SPICTRL_DELAYVAL_MASK) 51 #define TX39_SPICTRL_DELAYVAL_SET(cr, val) \ 52 ((cr) | (((val) << TX39_SPICTRL_DELAYVAL_SHIFT) & \ 53 (TX39_SPICTRL_DELAYVAL_MASK << TX39_SPICTRL_DELAYVAL_SHIFT))) 54 /* SPICLK Rate = 7.3728MHz/(BAUDRATE*2 + 2) */ 55 #define TX39_SPICTRL_BAUDRATE_SHIFT 8 56 #define TX39_SPICTRL_BAUDRATE_MASK 0xf 57 #define TX39_SPICTRL_BAUDRATE(cr) \ 58 (((cr) >> TX39_SPICTRL_BAUDRATE_SHIFT) & \ 59 TX39_SPICTRL_BAUDRATE_MASK) 60 #define TX39_SPICTRL_BAUDRATE_SET(cr, val) \ 61 ((cr) | (((val) << TX39_SPICTRL_BAUDRATE_SHIFT) & \ 62 (TX39_SPICTRL_BAUDRATE_MASK << TX39_SPICTRL_BAUDRATE_SHIFT))) 63 #define TX39_SPICTRL_PHAPOL 0x00000020 64 #define TX39_SPICTRL_CLKPOL 0x00000010 65 #define TX39_SPICTRL_WORD 0x00000004 66 #define TX39_SPICTRL_LSB 0x00000002 67 #define TX39_SPICTRL_ENSPI 0x00000001 68 69 /* 70 * SPI Transmitter Holding Register 71 */ 72 /* W */ 73 #define TX39_SPICTRL_TXDATA_SHIFT 0 74 #define TX39_SPICTRL_TXDATA_MASK 0xffff 75 #define TX39_SPICTRL_TXDATA_SET(cr, val) \ 76 ((cr) | (((val) << TX39_SPICTRL_TXDATA_SHIFT) & \ 77 (TX39_SPICTRL_TXDATA_MASK << TX39_SPICTRL_TXDATA_SHIFT))) 78 79 /* 80 * SPI Receiver Holding Register 81 */ 82 /* R */ 83 #define TX39_SPICTRL_RXDATA_SHIFT 8 84 #define TX39_SPICTRL_RXDATA_MASK 0xf 85 #define TX39_SPICTRL_RXDATA(cr) \ 86 (((cr) >> TX39_SPICTRL_RXDATA_SHIFT) & \ 87 TX39_SPICTRL_RXDATA_MASK) 88
Indexes created Mon Sep 29 03:10:08 GMT 2025