1 /* $NetBSD: octeon_gmxreg.h,v 1.7 2022/05/23 21:46:12 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * GMX Registers 31 */ 32 33 #ifndef _OCTEON_GMXREG_H_ 34 #define _OCTEON_GMXREG_H_ 35 36 #define GMX0_RX0_INT_REG 0x000 37 #define GMX0_RX0_INT_EN 0x008 38 #define GMX0_PRT0_CFG 0x010 39 #define GMX0_RX0_FRM_CTL 0x018 40 #define GMX0_RX0_FRM_CHK 0x020 41 #define GMX0_RX0_FRM_MIN 0x028 42 #define GMX0_RX0_FRM_MAX 0x030 43 #define GMX0_RX0_JABBER 0x038 44 #define GMX0_RX0_DECISION 0x040 45 #define GMX0_RX0_UDD_SKP 0x048 46 #define GMX0_RX0_STATS_CTL 0x050 47 #define GMX0_RX0_IFG 0x058 48 #define GMX0_RX0_RX_INBND 0x060 49 #define GMX0_RX0_STATS_PKTS 0x080 50 #define GMX0_RX0_STATS_OCTS 0x088 51 #define GMX0_RX0_STATS_PKTS_CTL 0x090 52 #define GMX0_RX0_STATS_OCTS_CTL 0x098 53 #define GMX0_RX0_STATS_PKTS_DMAC 0x0a0 54 #define GMX0_RX0_STATS_OCTS_DMAC 0x0a8 55 #define GMX0_RX0_STATS_PKTS_DRP 0x0b0 56 #define GMX0_RX0_STATS_OCTS_DRP 0x0b8 57 #define GMX0_RX0_STATS_PKTS_BAD 0x0c0 58 #define GMX0_RX0_ADR_CTL 0x100 59 #define GMX0_RX0_ADR_CAM_EN 0x108 60 #define GMX0_RX0_ADR_CAM0 0x180 61 #define GMX0_RX0_ADR_CAM1 0x188 62 #define GMX0_RX0_ADR_CAM2 0x190 63 #define GMX0_RX0_ADR_CAM3 0x198 64 #define GMX0_RX0_ADR_CAM4 0x1a0 65 #define GMX0_RX0_ADR_CAM5 0x1a8 66 #define GMX0_TX0_CLK 0x208 67 #define GMX0_TX0_THRESH 0x210 68 #define GMX0_TX0_APPEND 0x218 69 #define GMX0_TX0_SLOT 0x220 70 #define GMX0_TX0_BURST 0x228 71 #define GMX0_SMAC0 0x230 72 #define GMX0_TX0_PAUSE_PKT_TIME 0x238 73 #define GMX0_TX0_MIN_PKT 0x240 74 #define GMX0_TX0_PAUSE_PKT_INTERVAL 0x248 75 #define GMX0_TX0_SOFT_PAUSE 0x250 76 #define GMX0_TX0_PAUSE_TOGO 0x258 77 #define GMX0_TX0_PAUSE_ZERO 0x260 78 #define GMX0_TX0_STATS_CTL 0x268 79 #define GMX0_TX0_CTL 0x270 80 #define GMX0_TX0_STAT0 0x280 81 #define GMX0_TX0_STAT1 0x288 82 #define GMX0_TX0_STAT2 0x290 83 #define GMX0_TX0_STAT3 0x298 84 #define GMX0_TX0_STAT4 0x2a0 85 #define GMX0_TX0_STAT5 0x2a8 86 #define GMX0_TX0_STAT6 0x2b0 87 #define GMX0_TX0_STAT7 0x2b8 88 #define GMX0_TX0_STAT8 0x2c0 89 #define GMX0_TX0_STAT9 0x2c8 90 #define GMX0_BIST0 0x400 91 #define GMX0_RX_PRTS 0x410 92 #define GMX0_RX_BP_DROP0 0x420 93 #define GMX0_RX_BP_DROP1 0x428 94 #define GMX0_RX_BP_DROP2 0x430 95 #define GMX0_RX_BP_ON0 0x440 96 #define GMX0_RX_BP_ON1 0x448 97 #define GMX0_RX_BP_ON2 0x450 98 #define GMX0_RX_BP_OFF0 0x460 99 #define GMX0_RX_BP_OFF1 0x468 100 #define GMX0_RX_BP_OFF2 0x470 101 #define GMX0_TX_PRTS 0x480 102 #define GMX0_TX_IFG 0x488 103 #define GMX0_TX_JAM 0x490 104 #define GMX0_TX_COL_ATTEMPT 0x498 105 #define GMX0_TX_PAUSE_PKT_DMAC 0x4a0 106 #define GMX0_TX_PAUSE_PKT_TYPE 0x4a8 107 #define GMX0_TX_OVR_BP 0x4c8 108 #define GMX0_TX_BP 0x4d0 109 #define GMX0_TX_CORRUPT 0x4d8 110 #define GMX0_RX_PRT_INFO 0x4e8 111 #define GMX0_TX_LFSR 0x4f8 112 #define GMX0_TX_INT_REG 0x500 113 #define GMX0_TX_INT_EN 0x508 114 #define GMX0_NXA_ADR 0x510 115 #define GMX0_BAD_REG 0x518 116 #define GMX0_STAT_BP 0x520 117 #define GMX0_TX_CLK_MSK0 0x780 118 #define GMX0_TX_CLK_MSK1 0x788 119 #define GMX0_RX_TX_STATUS 0x7e8 120 #define GMX0_INF_MODE 0x7f8 121 122 /* -------------------------------------------------------------------------- */ 123 124 /* GMX Interrupt Registers */ 125 126 #define RXN_INT_REG_XXX_63_19 UINT64_C(0xfffffffffff80000) 127 #define RXN_INT_REG_PHY_DUPX UINT64_C(0x0000000000040000) 128 #define RXN_INT_REG_PHY_SPD UINT64_C(0x0000000000020000) 129 #define RXN_INT_REG_PHY_LINK UINT64_C(0x0000000000010000) 130 #define RXN_INT_REG_IFGERR UINT64_C(0x0000000000008000) 131 #define RXN_INT_REG_COLDET UINT64_C(0x0000000000004000) 132 #define RXN_INT_REG_FALERR UINT64_C(0x0000000000002000) 133 #define RXN_INT_REG_RSVERR UINT64_C(0x0000000000001000) 134 #define RXN_INT_REG_PCTERR UINT64_C(0x0000000000000800) 135 #define RXN_INT_REG_OVRERR UINT64_C(0x0000000000000400) 136 #define RXN_INT_REG_NIBERR UINT64_C(0x0000000000000200) 137 #define RXN_INT_REG_SKPERR UINT64_C(0x0000000000000100) 138 #define RXN_INT_REG_RCVERR UINT64_C(0x0000000000000080) 139 #define RXN_INT_REG_LENERR UINT64_C(0x0000000000000040) 140 #define RXN_INT_REG_ALNERR UINT64_C(0x0000000000000020) 141 #define RXN_INT_REG_FCSERR UINT64_C(0x0000000000000010) 142 #define RXN_INT_REG_JABBER UINT64_C(0x0000000000000008) 143 #define RXN_INT_REG_MAXERR UINT64_C(0x0000000000000004) 144 #define RXN_INT_REG_CAREXT UINT64_C(0x0000000000000002) 145 #define RXN_INT_REG_MINERR UINT64_C(0x0000000000000001) 146 147 /* GMX Interrupt-Enable Registers */ 148 149 #define RXN_INT_EN_XXX_63_19 UINT64_C(0xfffffffffff80000) 150 #define RXN_INT_EN_PHY_DUPX UINT64_C(0x0000000000040000) 151 #define RXN_INT_EN_PHY_SPD UINT64_C(0x0000000000020000) 152 #define RXN_INT_EN_PHY_LINK UINT64_C(0x0000000000010000) 153 #define RXN_INT_EN_IFGERR UINT64_C(0x0000000000008000) 154 #define RXN_INT_EN_COLDET UINT64_C(0x0000000000004000) 155 #define RXN_INT_EN_FALERR UINT64_C(0x0000000000002000) 156 #define RXN_INT_EN_RSVERR UINT64_C(0x0000000000001000) 157 #define RXN_INT_EN_PCTERR UINT64_C(0x0000000000000800) 158 #define RXN_INT_EN_OVRERR UINT64_C(0x0000000000000400) 159 #define RXN_INT_EN_NIBERR UINT64_C(0x0000000000000200) 160 #define RXN_INT_EN_SKPERR UINT64_C(0x0000000000000100) 161 #define RXN_INT_EN_RCVERR UINT64_C(0x0000000000000080) 162 #define RXN_INT_EN_LENERR UINT64_C(0x0000000000000040) 163 #define RXN_INT_EN_ALNERR UINT64_C(0x0000000000000020) 164 #define RXN_INT_EN_FCSERR UINT64_C(0x0000000000000010) 165 #define RXN_INT_EN_JABBER UINT64_C(0x0000000000000008) 166 #define RXN_INT_EN_MAXERR UINT64_C(0x0000000000000004) 167 #define RXN_INT_EN_CAREXT UINT64_C(0x0000000000000002) 168 #define RXN_INT_EN_MINERR UINT64_C(0x0000000000000001) 169 170 /* GMX Port Configuration Registers */ 171 172 #define PRTN_CFG_XXX_63_9 UINT64_C(0xfffffffffffffe00) 173 #define PRTN_CFG_SPEED_MSB UINT64_C(0x0000000000000100) 174 #define PRTN_CFG_XXX_7_4 UINT64_C(0x00000000000000f0) 175 #define PRTN_CFG_SLOTTIME UINT64_C(0x0000000000000008) 176 #define PRTN_CFG_DUPLEX UINT64_C(0x0000000000000004) 177 #define PRTN_CFG_SPEED UINT64_C(0x0000000000000002) 178 #define PRTN_CFG_EN UINT64_C(0x0000000000000001) 179 180 /* Frame Control Registers */ 181 182 #define RXN_FRM_CTL_XXX_63_11 UINT64_C(0xfffffffffffff800) 183 #define RXN_FRM_CTL_NULL_DIS UINT64_C(0x0000000000000400) 184 #define RXN_FRM_CTL_PRE_ALIGN UINT64_C(0x0000000000000200) 185 #define RXN_FRM_CTL_PAD_LEN UINT64_C(0x0000000000000100) 186 #define RXN_FRM_CTL_VLAN_LEN UINT64_C(0x0000000000000080) 187 #define RXN_FRM_CTL_PRE_FREE UINT64_C(0x0000000000000040) 188 #define RXN_FRM_CTL_CTL_SMAC UINT64_C(0x0000000000000020) 189 #define RXN_FRM_CTL_CTL_MCST UINT64_C(0x0000000000000010) 190 #define RXN_FRM_CTL_CTL_BCK UINT64_C(0x0000000000000008) 191 #define RXN_FRM_CTL_CTL_DRP UINT64_C(0x0000000000000004) 192 #define RXN_FRM_CTL_PRE_STRP UINT64_C(0x0000000000000002) 193 #define RXN_FRM_CTL_PRE_CHK UINT64_C(0x0000000000000001) 194 195 /* Frame Check Registers */ 196 197 #define RXN_FRM_CKK_XXX_63_10 UINT64_C(0xfffffffffffffc00) 198 #define RXN_FRM_CHK_NIBERR UINT64_C(0x0000000000000200) 199 #define RXN_FRM_CHK_SKPERR UINT64_C(0x0000000000000100) 200 #define RXN_FRM_CHK_RCVERR UINT64_C(0x0000000000000080) 201 #define RXN_FRM_CHK_LENERR UINT64_C(0x0000000000000040) 202 #define RXN_FRM_CHK_ALNERR UINT64_C(0x0000000000000020) 203 #define RXN_FRM_CHK_FCSERR UINT64_C(0x0000000000000010) 204 #define RXN_FRM_CHK_JABBER UINT64_C(0x0000000000000008) 205 #define RXN_FRM_CHK_MAXERR UINT64_C(0x0000000000000004) 206 #define RXN_FRM_CHK_CAREXT UINT64_C(0x0000000000000002) 207 #define RXN_FRM_CHK_MINERR UINT64_C(0x0000000000000001) 208 209 /* Frame Minimum-Length Registers */ 210 211 #define RXN_RRM_MIN_XXX_63_16 UINT64_C(0xffffffffffff0000) 212 #define RXN_RRM_MIN_LEN UINT64_C(0x000000000000ffff) 213 214 /* Frame Maximun-Length Registers */ 215 216 #define RXN_RRM_MAX_XXX_63_16 UINT64_C(0xffffffffffff0000) 217 #define RXN_RRM_MAX_LEN UINT64_C(0x000000000000ffff) 218 219 /* GMX Maximun Packet-Size Registers */ 220 221 #define RXN_JABBER_XXX_63_16 UINT64_C(0xffffffffffff0000) 222 #define RXN_JABBER_CNT UINT64_C(0x000000000000ffff) 223 224 /* GMX Packet Decision Registers */ 225 226 #define RXN_DECISION_XXX_63_5 UINT64_C(0xffffffffffffffe0) 227 #define RXN_DECISION_CNT UINT64_C(0x000000000000001f) 228 229 /* GMX User-Defined Data Skip Registers */ 230 231 #define RXN_UDD_SKP_XXX_63_9 UINT64_C(0xfffffffffffffe00) 232 #define RXN_UDD_SKP_FCSSEL UINT64_C(0x0000000000000100) 233 #define RXN_UDD_SKP_XXX_7 UINT64_C(0x0000000000000080) 234 #define RXN_UDD_SKP_LEN UINT64_C(0x000000000000007f) 235 236 /* GMX RX Statistics Control Registers */ 237 238 #define RXN_STATS_CTL_XXX_63_1 UINT64_C(0xfffffffffffffffe) 239 #define RXN_STATS_CTL_RD_CLR UINT64_C(0x0000000000000001) 240 241 /* GMX Minimum Interface-Gap Cycles Registers */ 242 243 #define RXN_IFG_XXX_63_4 UINT64_C(0xfffffffffffffff0) 244 #define RXN_IFG_IFG UINT64_C(0x000000000000000f) 245 246 /* InBand Link Status Registers */ 247 248 #define RXN_RX_INBND_XXX_63_4 UINT64_C(0xfffffffffffffff0) 249 #define RXN_RX_INBND_DUPLEX UINT64_C(0x0000000000000008) 250 #define RXN_RX_INBND_DUPLEX_HALF 0 251 #define RXN_RX_INBND_DUPLEX_FULL 1 252 #define RXN_RX_INBND_SPEED UINT64_C(0x0000000000000006) 253 #define RXN_RX_INBND_SPEED_2_5 0 254 #define RXN_RX_INBND_SPEED_25 1 255 #define RXN_RX_INBND_SPEED_125 2 256 #define RXN_RX_INBND_SPEED_XXX_3 3 257 #define RXN_RX_INBND_STATUS UINT64_C(0x0000000000000001) 258 259 /* GMX RX Good Packets Registers */ 260 261 #define RXN_STATS_PKTS_XXX_63_32 UINT64_C(0xffffffff00000000) 262 #define RXN_STATS_PKTS_CNT UINT64_C(0x00000000ffffffff) 263 264 /* GMX RX Good Packets Octet Registers */ 265 266 #define RXN_STATS_OCTS_XXX_63_48 UINT64_C(0xffff000000000000) 267 #define RXN_STATS_OCTS_CNT UINT64_C(0x0000ffffffffffff) 268 269 /* GMX RX Pause Packets Registers */ 270 271 #define RXN_STATS_PKTS_CTL_XXX_63_32 UINT64_C(0xffffffff00000000) 272 #define RXN_STATS_PKTS_CTL_CNT UINT64_C(0x00000000ffffffff) 273 274 /* GMX RX Pause Packets Octet Registers */ 275 276 #define RXN_STATS_OCTS_CTL_XXX_63_48 UINT64_C(0xffff000000000000) 277 #define RXN_STATS_OCTS_CTL_CNT UINT64_C(0x0000ffffffffffff) 278 279 /* GMX RX DMAC Packets Registers */ 280 281 #define RXN_STATS_PKTS_DMAC_XXX_63_32 UINT64_C(0xffffffff00000000) 282 #define RXN_STATS_PKTS_DMAC_CNT UINT64_C(0x00000000ffffffff) 283 284 /* GMX RX DMAC Packets Octet Registers */ 285 286 #define RXN_STATS_OCTS_DMAC_XXX_63_48 UINT64_C(0xffff000000000000) 287 #define RXN_STATS_OCTS_DMAC_CNT UINT64_C(0x0000ffffffffffff) 288 289 /* GMX RX Overflow Packets Registers */ 290 291 #define RXN_STATS_PKTS_DRP_XXX_63_48 UINT64_C(0xffffffff00000000) 292 #define RXN_STATS_PKTS_DRP_CNT UINT64_C(0x00000000ffffffff) 293 294 /* GMX RX Overflow Packets Octet Registers */ 295 296 #define RXN_STATS_OCTS_DRP_XXX_63_48 UINT64_C(0xffff000000000000) 297 #define RXN_STATS_OCTS_DRP_CNT UINT64_C(0x0000ffffffffffff) 298 299 /* GMX RX Bad Packets Registers */ 300 301 #define RXN_STATS_PKTS_BAD_XXX_63_48 UINT64_C(0xffffffff00000000) 302 #define RXN_STATS_PKTS_BAD_CNT UINT64_C(0x00000000ffffffff) 303 304 /* Address-Filtering Control Registers */ 305 306 #define RXN_ADR_CTL_XXX_63_4 UINT64_C(0xfffffffffffffff0) 307 #define RXN_ADR_CTL_CAM_MODE UINT64_C(0x0000000000000008) 308 #define RXN_ADR_CTL_CAM_MODE_REJECT 0 309 #define RXN_ADR_CTL_CAM_MODE_ACCEPT 1 310 #define RXN_ADR_CTL_MCST UINT64_C(0x0000000000000006) 311 #define RXN_ADR_CTL_MCST_AFCAM 0 312 #define RXN_ADR_CTL_MCST_REJECT 1 313 #define RXN_ADR_CTL_MCST_ACCEPT 2 314 #define RXN_ADR_CTL_MCST_XXX_3 3 315 #define RXN_ADR_CTL_BCST UINT64_C(0x0000000000000001) 316 317 /* Address-Filtering Control Enable Registers */ 318 319 #define RXN_ADR_CAM_EN_XXX_63_8 UINT64_C(0xffffffffffffff00) 320 #define RXN_ADR_CAM_EN_EN UINT64_C(0x00000000000000ff) 321 322 /* Address-Filtering CAM Control Registers */ 323 #define RXN_ADR_CAMN_ADR UINT64_C(0xffffffffffffffff) 324 325 /* GMX TX Clock Generation Registers */ 326 327 #define TXN_CLK_XXX_63_6 UINT64_C(0xffffffffffffffc0) 328 #define TXN_CLK_CLK_CNT UINT64_C(0x000000000000003f) 329 330 /* TX Threshold Registers */ 331 332 #define TXN_THRESH_XXX_63_6 UINT64_C(0xffffffffffffffc0) 333 #define TXN_THRESH_CNT UINT64_C(0x000000000000003f) 334 335 /* TX Append Control Registers */ 336 337 #define TXN_APPEND_XXX_63_4 UINT64_C(0xfffffffffffffff0) 338 #define TXN_APPEND_FORCE_FCS UINT64_C(0x0000000000000008) 339 #define TXN_APPEND_FCS UINT64_C(0x0000000000000004) 340 #define TXN_APPEND_PAD UINT64_C(0x0000000000000002) 341 #define TXN_APPEND_PREAMBLE UINT64_C(0x0000000000000001) 342 343 /* TX Slottime Counter Registers */ 344 345 #define TXN_SLOT_XXX_63_10 UINT64_C(0xfffffffffffffc00) 346 #define TXN_SLOT_SLOT UINT64_C(0x00000000000003ff) 347 348 /* TX Burst-Counter Registers */ 349 350 #define TXN_BURST_XXX_63_16 UINT64_C(0xffffffffffff0000) 351 #define TXN_BURST_BURST UINT64_C(0x000000000000ffff) 352 353 /* RGMII SMAC Registers */ 354 355 #define SMACN_XXX_63_48 UINT64_C(0xffff000000000000) 356 #define SMACN_SMAC UINT64_C(0x0000ffffffffffff) 357 358 /* TX Pause Packet Pause-Time Registers */ 359 360 #define TXN_PAUSE_PKT_TIME_XXX_63_16 UINT64_C(0xffffffffffff0000) 361 #define TXN_PAUSE_PKT_TIME_TIME UINT64_C(0x000000000000ffff) 362 363 /* RGMII TX Minimum-Size-Packet Registers */ 364 365 #define TXN_MIN_PKT_XXX_63_8 UINT64_C(0xffffffffffffff00) 366 #define TXN_MIN_PKT_MIN_SIZE UINT64_C(0x00000000000000ff) 367 368 /* TX Pause-Packet Transmission-Interval Registers */ 369 370 #define TXN_PAUSE_PKT_INTERVAL_XXX_63_16 UINT64_C(0xffffffffffff0000) 371 #define TXN_PAUSE_PKT_INTERVAL_INTERVAL UINT64_C(0x000000000000ffff) 372 373 /* TX Software-Pause Registers */ 374 375 #define TXN_SOFT_PAUSE_XXX_63_16 UINT64_C(0xffffffffffff0000) 376 #define TXN_SOFT_PAUSE_TIME UINT64_C(0x000000000000ffff) 377 378 /* TX Time-to-Backpressure Registers */ 379 380 #define TXN_PAUSE_TOGO_XXX_63_16 UINT64_C(0xffffffffffff0000) 381 #define TXN_PAUSE_TOGO_TIME UINT64_C(0x000000000000ffff) 382 383 /* TX Pause-Zero-Enable Registers */ 384 385 #define TXN_PAUSE_ZERO_XXX_63_1 UINT64_C(0xfffffffffffffffe) 386 #define TXN_PAUSE_ZERO_SEND UINT64_C(0x0000000000000001) 387 388 /* GMX TX Statistics Control Registers */ 389 390 #define TXN_STATS_CTL_XXX_63_1 UINT64_C(0xfffffffffffffffe) 391 #define TXN_STATS_CTL_RD_CLR UINT64_C(0x0000000000000001) 392 393 /* GMX TX Transmit Control Registers */ 394 395 #define TXN_CTL_XXX_63_2 UINT64_C(0xfffffffffffffffc) 396 #define TXN_CTL_XSDEF_EN UINT64_C(0x0000000000000002) 397 #define TXN_CTL_XSCOL_EN UINT64_C(0x0000000000000001) 398 399 /* Transmit Statistics Registers 0 */ 400 401 #define TXN_STAT0_XSDEF UINT64_C(0xffffffff00000000) 402 #define TXN_STAT0_XSCOL UINT64_C(0x00000000ffffffff) 403 404 /* Transmit Statistics Registers 1 */ 405 406 #define TXN_STAT1_SCOL UINT64_C(0xffffffff00000000) 407 #define TXN_STAT1_MSCOL UINT64_C(0x00000000ffffffff) 408 409 /* Transmit Statistics Registers 2 */ 410 411 #define TXN_STAT2_XXX_63_48 UINT64_C(0xffff000000000000) 412 #define TXN_STAT2_OCTS UINT64_C(0x0000ffffffffffff) 413 414 /* Transmit Statistics Registers 3 */ 415 416 #define TXN_STAT3_XXX_63_48 UINT64_C(0xffffffff00000000) 417 #define TXN_STAT3_PKTS UINT64_C(0x00000000ffffffff) 418 419 /* Transmit Statistics Registers 4 */ 420 421 #define TXN_STAT4_HIST1 UINT64_C(0xffffffff00000000) 422 #define TXN_STAT4_HIST0 UINT64_C(0x00000000ffffffff) 423 424 /* Transmit Statistics Registers 5 */ 425 426 #define TXN_STAT5_HIST3 UINT64_C(0xffffffff00000000) 427 #define TXN_STAT5_HIST2 UINT64_C(0x00000000ffffffff) 428 429 /* Transmit Statistics Registers 6 */ 430 431 #define TXN_STAT6_HIST5 UINT64_C(0xffffffff00000000) 432 #define TXN_STAT6_HIST4 UINT64_C(0x00000000ffffffff) 433 434 /* Transmit Statistics Registers 7 */ 435 436 #define TXN_STAT7_HIST7 UINT64_C(0xffffffff00000000) 437 #define TXN_STAT7_HIST6 UINT64_C(0x00000000ffffffff) 438 439 /* Transmit Statistics Registers 8 */ 440 441 #define TXN_STAT8_MCST UINT64_C(0xffffffff00000000) 442 #define TXN_STAT8_BCST UINT64_C(0x00000000ffffffff) 443 444 /* Transmit Statistics Register 9 */ 445 446 #define TXN_STAT9_UNDFLW UINT64_C(0xffffffff00000000) 447 #define TXN_STAT9_CTL UINT64_C(0x00000000ffffffff) 448 449 /* BMX BIST Results Register */ 450 451 #define BIST_XXX_63_10 UINT64_C(0xfffffffffffffc00) 452 #define BIST_STATUS UINT64_C(0x00000000000003ff) 453 454 /* RX Ports Register */ 455 456 #define RX_PRTS_XXX_63_3 UINT64_C(0xfffffffffffffff8) 457 #define RX_PRTS_PRTS UINT64_C(0x0000000000000007) 458 459 /* RX FIFO Packet-Drop Registers */ 460 461 #define RX_BP_DROPN_XXX_63_6 UINT64_C(0xffffffffffffffc0) 462 #define RX_BP_DROPN_MARK UINT64_C(0x000000000000003f) 463 464 /* RX Backpressure On Registers */ 465 466 #define RX_BP_ONN_XXX_63_9 UINT64_C(0xfffffffffffffe00) 467 #define RX_BP_ONN_MARK UINT64_C(0x00000000000001ff) 468 469 /* RX Backpressure Off Registers */ 470 471 #define RX_BP_OFFN_XXX_63_6 UINT64_C(0xffffffffffffffc0) 472 #define RX_BP_OFFN_MARK UINT64_C(0x000000000000003f) 473 474 /* TX Ports Register */ 475 476 #define TX_PRTS_XXX_63_5 UINT64_C(0xffffffffffffffe0) 477 #define TX_PRTS_PRTS UINT64_C(0x000000000000001f) 478 479 /* TX Interframe Gap Register */ 480 481 #define TX_IFG_XXX_63_8 UINT64_C(0xffffffffffffff00) 482 #define TX_IFG_IFG2 UINT64_C(0x00000000000000f0) 483 #define TX_IFG_IFG1 UINT64_C(0x000000000000000f) 484 485 /* TX Jam Pattern Register */ 486 487 #define TX_JAM_XXX_63_8 UINT64_C(0xffffffffffffff00) 488 #define TX_JAM_JAM UINT64_C(0x00000000000000ff) 489 490 /* TX Collision Attempts Before Dropping Frame Register */ 491 492 #define TX_COL_ATTEMPT_XXX_63_5 UINT64_C(0xffffffffffffffe0) 493 #define TX_COL_ATTEMPT_LIMIT UINT64_C(0x000000000000001f) 494 495 /* TX Pause-Packet DMAC-Field Register */ 496 497 #define TX_PAUSE_PKT_DMAC_XXX_63_48 UINT64_C(0xffff000000000000) 498 #define TX_PAUSE_PKT_DMAC_DMAC UINT64_C(0x0000ffffffffffff) 499 500 /* TX Pause Packet Type Field Register */ 501 502 #define TX_PAUSE_PKT_TYPE_XXX_63_16 UINT64_C(0xffffffffffff0000) 503 #define TX_PAUSE_PKT_TYPE_TYPE UINT64_C(0x000000000000ffff) 504 505 /* TX Override Backpressure Register */ 506 507 #define TX_OVR_BP_XXX_63_12 UINT64_C(0xfffffffffffff000) 508 #define TX_OVR_BP_XXX_11 UINT64_C(0x0000000000000800) 509 #define TX_OVR_BP_EN UINT64_C(0x0000000000000700) 510 #define TX_OVR_BP_XXX_7 UINT64_C(0x0000000000000080) 511 #define TX_OVR_BP_BP UINT64_C(0x0000000000000070) 512 #define TX_OVR_BP_XXX_3 UINT64_C(0x0000000000000008) 513 #define TX_OVR_BP_IGN_FULL UINT64_C(0x0000000000000007) 514 515 /* TX Override Backpressure Register */ 516 517 #define TX_OVR_BP_XXX_63_12 UINT64_C(0xfffffffffffff000) 518 #define TX_OVR_BP_XXX_11 UINT64_C(0x0000000000000800) 519 #define TX_OVR_BP_EN UINT64_C(0x0000000000000700) 520 #define TX_OVR_BP_XXX_7 UINT64_C(0x0000000000000080) 521 #define TX_OVR_BP_BP UINT64_C(0x0000000000000070) 522 #define TX_OVR_BP_XXX_3 UINT64_C(0x0000000000000008) 523 #define TX_OVR_BP_IGN_FULL UINT64_C(0x0000000000000007) 524 525 /* TX Backpressure Status Register */ 526 527 #define TX_BP_SR_XXX_63_3 UINT64_C(0xfffffffffffffff8) 528 #define TX_BP_SR_BP UINT64_C(0x0000000000000007) 529 530 /* TX Corrupt Packets Register */ 531 532 #define TX_CORRUPT_XXX_63_3 UINT64_C(0xfffffffffffffff8) 533 #define TX_CORRUPT_CORRUPT UINT64_C(0x0000000000000007) 534 535 /* RX Port State Information Register */ 536 537 #define RX_PRT_INFO_XXX_63_19 UINT64_C(0xfffffffffff80000) 538 #define RX_PRT_INFO_DROP UINT64_C(0x0000000000070000) 539 #define RX_PRT_INFO_XXX_15_3 UINT64_C(0x000000000000fff8) 540 #define RX_PRT_INFO_COMMIT UINT64_C(0x0000000000000007) 541 542 /* TX LFSR Register */ 543 544 #define TX_LFSR_XXX_63_16 UINT64_C(0xffffffffffff0000) 545 #define TX_LFSR_LFSR UINT64_C(0x000000000000ffff) 546 547 /* TX Interrupt Register */ 548 549 #define TX_INT_REG_XXX_63_20 UINT64_C(0xfffffffffff00000) 550 #define TX_INT_REG_XXX_19 UINT64_C(0x0000000000080000) 551 #define TX_INT_REG_LATE_COL UINT64_C(0x0000000000070000) 552 #define TX_INT_REG_XXX_15 UINT64_C(0x0000000000008000) 553 #define TX_INT_REG_XSDEF UINT64_C(0x0000000000007000) 554 #define TX_INT_REG_XXX_11 UINT64_C(0x0000000000000800) 555 #define TX_INT_REG_XSCOL UINT64_C(0x0000000000000700) 556 #define TX_INT_REG_XXX_7_5 UINT64_C(0x00000000000000e0) 557 #define TX_INT_REG_UNDFLW UINT64_C(0x000000000000001c) 558 #define TX_INT_REG_XXX_1 UINT64_C(0x0000000000000002) 559 #define TX_INT_REG_PKO_NXA UINT64_C(0x0000000000000001) 560 561 /* TX Interrupt Register */ 562 563 #define TX_INT_EN_XXX_63_20 UINT64_C(0xfffffffffff00000) 564 #define TX_INT_EN_XXX_19 UINT64_C(0x0000000000080000) 565 #define TX_INT_EN_LATE_COL UINT64_C(0x0000000000070000) 566 #define TX_INT_EN_XXX_15 UINT64_C(0x0000000000008000) 567 #define TX_INT_EN_XSDEF UINT64_C(0x0000000000007000) 568 #define TX_INT_EN_XXX_11 UINT64_C(0x0000000000000800) 569 #define TX_INT_EN_XSCOL UINT64_C(0x0000000000000700) 570 #define TX_INT_EN_XXX_7_5 UINT64_C(0x00000000000000e0) 571 #define TX_INT_EN_UNDFLW UINT64_C(0x000000000000001c) 572 #define TX_INT_EN_XXX_1 UINT64_C(0x0000000000000002) 573 #define TX_INT_EN_PKO_NXA UINT64_C(0x0000000000000001) 574 575 /* Address-out-of-Range Error Register */ 576 577 #define NXA_ADR_XXX_63_6 UINT64_C(0xffffffffffffffc0) 578 #define NXA_ADR_PRT UINT64_C(0x000000000000003f) 579 580 /* GMX Miscellaneous Error Register */ 581 582 #define BAD_REG_XXX_63_31 UINT64_C(0xffffffff80000000) 583 #define BAD_REG_INB_NXA UINT64_C(0x0000000078000000) 584 #define BAD_REG_STATOVR UINT64_C(0x0000000004000000) 585 #define BAD_REG_XXX_25 UINT64_C(0x0000000002000000) 586 #define BAD_REG_LOSTSTAT UINT64_C(0x0000000001c00000) 587 #define BAD_REG_XXX_21_18 UINT64_C(0x00000000003c0000) 588 #define BAD_REG_XXX_17_5 UINT64_C(0x000000000003ffe0) 589 #define BAD_REG_OUT_OVR UINT64_C(0x000000000000001c) 590 #define BAD_REG_XXX_1_0 UINT64_C(0x0000000000000003) 591 592 /* GMX Backpressure Statistics Register */ 593 594 #define STAT_BP_XXX_63_17 UINT64_C(0xfffffffffffe0000) 595 #define STAT_BP_BP UINT64_C(0x0000000000010000) 596 #define STAT_BP_CNT UINT64_C(0x000000000000ffff) 597 598 /* Mode Change Mask Registers */ 599 600 #define TX_CLK_MSKN_XXX_63_1 UINT64_C(0xfffffffffffffffe) 601 #define TX_CLK_MSKN_MSK UINT64_C(0x0000000000000001) 602 603 /* GMX RX/TX Status Register */ 604 605 #define RX_TX_STATUS_XXX_63_7 UINT64_C(0xffffffffffffff80) 606 #define RX_TX_STATUS_TX UINT64_C(0x0000000000000070) 607 #define RX_TX_STATUS_XXX_3 UINT64_C(0x0000000000000008) 608 #define RX_TX_STATUS_RX UINT64_C(0x0000000000000007) 609 610 /* Interface Mode Register */ 611 612 #define INF_MODE_XXX_63_3 UINT64_C(0xfffffffffffffff8) 613 #define INF_MODE_P0MII UINT64_C(0x0000000000000004) 614 #define INF_MODE_EN UINT64_C(0x0000000000000002) 615 #define INF_MODE_TYPE UINT64_C(0x0000000000000001) 616 /* Interface mode, applicable on CN68xx and CN7xxx (?) */ 617 #define INF_MODE_MODE UINT64_C(0x0000000000000070) 618 #define INF_MODE_MODE_SGMII UINT64_C(0x0000000000000020) 619 #define INF_MODE_MODE_XAUI UINT64_C(0x0000000000000030) 620 621 #define MIO_QLM_CFG(x) (UINT64_C(0x0001180000001590) + (x)*8) 622 623 #define MIO_QLM_CFG_CFG UINT64_C(0x000000000000000f) 624 625 /* -------------------------------------------------------------------------- */ 626 627 /* for bus_space(9) */ 628 629 #define GMX_PORT_NUNITS (5 * 16) 630 #define GMX_PORT_NUM(g, i) ((g) * 16 + (i)) 631 #define GMX_PORT_IFACE(port) ((port) / 16) 632 #define GMX_PORT_INDEX(port) ((port) % 16) 633 634 #define GMX_BLOCK_SIZE 0x8000000 635 #define GMX_CN68XX_BLOCK_SIZE 0x100000 /* different on CN68XX only */ 636 637 #define GMX0_BASE_PORT0 UINT64_C(0x0001180008000000) 638 #define GMX_PORT_SIZE 0x800 639 #define GMX_IF_SIZE(n) (GMX_PORT_SIZE * (n)) 640 #define GMX_BASE_PORT(n, m) /* address of GMX(n) * PORT(m) */ \ 641 (GMX0_BASE_PORT0 + (n) * GMX_BLOCK_SIZE + GMX_IF_SIZE(m)) 642 #define GMX_CN68XX_BASE_PORT(n, m) /* address of GMX(n) * PORT(m) */ \ 643 (GMX0_BASE_PORT0 + (n) * GMX_CN68XX_BLOCK_SIZE + GMX_IF_SIZE(m)) 644 645 /* -------------------------------------------------------------------------- */ 646 647 /* Low-level SGMII link control */ 648 649 #define PCS_BASE(g, i) (UINT64_C(0x00011800b0001000) + 0x8000000 * (g) + 0x400 * (i)) 650 #define PCS_SIZE 0x98 651 652 #define PCS_MR_CONTROL 0x00 653 #define PCS_MR_STATUS 0x08 654 #define PCS_LINK_TIMER_COUNT 0x40 655 #define PCS_MISC_CTL 0x78 656 657 #define PCS_MR_CONTROL_RES_16_63 UINT64_C(0xffffffffffff0000) 658 #define PCS_MR_CONTROL_RESET UINT64_C(0x0000000000008000) 659 #define PCS_MR_CONTROL_LOOPBCK1 UINT64_C(0x0000000000004000) 660 #define PCS_MR_CONTROL_SPDLSB UINT64_C(0x0000000000002000) 661 #define PCS_MR_CONTROL_AN_EN UINT64_C(0x0000000000001000) 662 #define PCS_MR_CONTROL_PWR_DN UINT64_C(0x0000000000000800) 663 #define PCS_MR_CONTROL_RES_10_10 UINT64_C(0x0000000000000400) 664 #define PCS_MR_CONTROL_RST_AN UINT64_C(0x0000000000000200) 665 #define PCS_MR_CONTROL_DUPLEX UINT64_C(0x0000000000000100) 666 #define PCS_MR_CONTROL_COLTST UINT64_C(0x0000000000000080) 667 #define PCS_MR_CONTROL_SPDMSB UINT64_C(0x0000000000000040) 668 #define PCS_MR_CONTROL_UNI UINT64_C(0x0000000000000020) 669 #define PCS_MR_CONTROL_RES_0_4 UINT64_C(0x000000000000001f) 670 671 #define PCS_MR_STATUS_RES_16_63 UINT64_C(0xffffffffffff0000) 672 #define PCS_MR_STATUS_HUN_T4 UINT64_C(0x0000000000008000) 673 #define PCS_MR_STATUS_HUN_XFD UINT64_C(0x0000000000004000) 674 #define PCS_MR_STATUS_HUN_XHD UINT64_C(0x0000000000002000) 675 #define PCS_MR_STATUS_TEN_FD UINT64_C(0x0000000000001000) 676 #define PCS_MR_STATUS_TEN_HD UINT64_C(0x0000000000000800) 677 #define PCS_MR_STATUS_HUN_T2FD UINT64_C(0x0000000000000400) 678 #define PCS_MR_STATUS_HUN_T2HD UINT64_C(0x0000000000000200) 679 #define PCS_MR_STATUS_EXT_ST UINT64_C(0x0000000000000100) 680 #define PCS_MR_STATUS_RES_7_7 UINT64_C(0x0000000000000080) 681 #define PCS_MR_STATUS_PRB_SUP UINT64_C(0x0000000000000040) 682 #define PCS_MR_STATUS_AN_CPT UINT64_C(0x0000000000000020) 683 #define PCS_MR_STATUS_RM_FLT UINT64_C(0x0000000000000010) 684 #define PCS_MR_STATUS_AN_ABIL UINT64_C(0x0000000000000008) 685 #define PCS_MR_STATUS_LNK_ST UINT64_C(0x0000000000000004) 686 #define PCS_MR_STATUS_RES_1_1 UINT64_C(0x0000000000000002) 687 #define PCS_MR_STATUS_EXTND UINT64_C(0x0000000000000001) 688 689 #define PCS_LINK_TIMER_COUNT_MASK UINT64_C(0x000000000000ffff) 690 691 #define PCS_MISC_CTL_SGMII UINT64_C(0x0000000000001000) 692 #define PCS_MISC_CTL_GMXENO UINT64_C(0x0000000000000800) 693 #define PCS_MISC_CTL_LOOPBCK2 UINT64_C(0x0000000000000400) 694 #define PCS_MISC_CTL_MAC_PHY UINT64_C(0x0000000000000200) 695 #define PCS_MISC_CTL_MODE UINT64_C(0x0000000000000100) 696 #define PCS_MISC_CTL_AN_OVRD UINT64_C(0x0000000000000080) 697 #define PCS_MISC_CTL_SAMP_PT UINT64_C(0x000000000000007f) 698 699 #endif /* _OCTEON_GMXREG_H_ */ 700
Indexes created Tue Sep 23 14:10:03 GMT 2025