1 /* 2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. 3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sub license, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _VIA_ENG_REGS_H_ 26 #define _VIA_H_ 1 27 28 #include <errno.h> 29 #include <string.h> 30 #include <stdio.h> 31 #include <math.h> 32 #include <assert.h> 33 #include <stdlib.h> 34 35 /* Video status flag */ 36 37 #define VIDEO_HIDE 0x00000000 /*Video off*/ 38 #define VIDEO_SHOW 0x80000000 /*Video on*/ 39 #define VIDEO_ACTIVE 0x10000000 /*Video active*/ 40 #define VIDEO_MPEG_INUSE 0x08000000 /*Video is used with MPEG */ 41 #define VIDEO_HQV_INUSE 0x04000000 /*Video is used with HQV*/ 42 #define VIDEO_CAPTURE0_INUSE 0x02000000 /*Video is used with CAPTURE 0*/ 43 #define VIDEO_CAPTURE1_INUSE 0x00000000 /*Video is used with CAPTURE 1*/ 44 #define VIDEO_1_INUSE 0x01000000 /*Video 1 is used with software flip*/ 45 #define VIDEO_3_INUSE 0x00000000 /*Video 3 is used with software flip*/ 46 #define VIDEO_ON 0x00100000 47 #define MPEG_USE_V1 0x00010000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/ 48 #define MPEG_USE_V3 0x00000000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/ 49 #define MPEG_USE_HQV 0x00020000 /*[17] : 1:MPEG use HQV,0:MPEG not use HQV*/ 50 #define MPEG_USE_HW_FLIP 0x00040000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/ 51 #define MPEG_USE_SW_FLIP 0x00000000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/ 52 #define CAP0_USE_V1 0x00001000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/ 53 #define CAP0_USE_V3 0x00000000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/ 54 #define CAP0_USE_HQV 0x00002000 /*[13] : 1:Capture 0 use HQV,0:Capture 0 not use HQV*/ 55 #define CAP0_USE_HW_FLIP 0x00004000 /*[14] : 1:Capture 0 use H/W flip,0:Capture 0 use S/W flip*/ 56 #define CAP0_USE_CCIR656 0x00008000 /*[15] : 1:Capture 0 use CCIR656,0:Capture 0 CCIR601*/ 57 #define CAP1_USE_V1 0x00000100 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/ 58 #define CAP1_USE_V3 0x00000000 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/ 59 #define CAP1_USE_HQV 0x00000200 /*[ 9] : 1:Capture 1 use HQV,0:Capture 1 not use HQV*/ 60 #define CAP1_USE_HW_FLIP 0x00000400 /*[10] : 1:Capture 1 use H/W flip,0:Capture 1 use S/W flip */ 61 #define SW_USE_V1 0x00000010 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */ 62 #define SW_USE_V3 0x00000000 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */ 63 #define SW_USE_HQV 0x00000020 /*[ 5] : 1:Capture 1 use HQV,0:Capture 1 not use HQV */ 64 65 /* 66 #define VIDEO1_INUSE 0x00000010 //[ 4] : 1:Video 1 is used with S/W flip 67 #define VIDEO1_USE_HQV 0x00000020 //[ 5] : 1:Video 1 use HQV with S/W flip 68 #define VIDEO3_INUSE 0x00000001 //[ 0] : 1:Video 3 is used with S/W flip 69 #define VIDEO3_USE_HQV 0x00000002 //[ 1] : 1:Video 3 use HQV with S/W flip 70 */ 71 72 /* H/W registers for Video Engine */ 73 74 /* 75 * bus master 76 */ 77 #define PCI_MASTER_ENABLE 0x01 78 #define PCI_MASTER_SCATTER 0x00 79 #define PCI_MASTER_SINGLE 0x02 80 #define PCI_MASTER_GUI 0x00 81 #define PCI_MASTER_VIDEO 0x04 82 #define PCI_MASTER_INPUT 0x00 83 #define PCI_MASTER_OUTPUT 0x08 84 85 /* 86 * video registers 87 */ 88 #define V_FLAGS 0x200 89 #define V_CAP_STATUS 0x204 90 #define V_FLIP_STATUS 0x204 91 #define V_ALPHA_WIN_START 0x208 92 #define V_ALPHA_WIN_END 0x20C 93 #define V_ALPHA_CONTROL 0x210 94 #define V_CRT_STARTADDR 0x214 95 #define V_CRT_STARTADDR_2 0x218 96 #define V_ALPHA_STRIDE 0x21C 97 #define V_COLOR_KEY 0x220 98 #define V_ALPHA_STARTADDR 0x224 99 #define V_CHROMAKEY_LOW 0x228 100 #define V_CHROMAKEY_HIGH 0x22C 101 #define V1_CONTROL 0x230 102 #define V12_QWORD_PER_LINE 0x234 103 #define V1_STARTADDR_1 0x238 104 #define V1_STARTADDR_Y1 V1_STARTADDR_1 105 #define V1_STRIDE 0x23C 106 #define V1_WIN_START_Y 0x240 107 #define V1_WIN_START_X 0x242 108 #define V1_WIN_END_Y 0x244 109 #define V1_WIN_END_X 0x246 110 #define V1_STARTADDR_2 0x248 111 #define V1_STARTADDR_Y2 V1_STARTADDR_2 112 #define V1_ZOOM_CONTROL 0x24C 113 #define V1_MINI_CONTROL 0x250 114 #define V1_STARTADDR_0 0x254 115 #define V1_STARTADDR_Y0 V1_STARTADDR_0 116 #define V_FIFO_CONTROL 0x258 117 #define V1_STARTADDR_3 0x25C 118 #define V1_STARTADDR_Y3 V1_STARTADDR_3 119 #define HI_CONTROL 0x260 120 #define SND_COLOR_KEY 0x264 121 #define ALPHA_V3_PREFIFO_CONTROL 0x268 122 #define V1_SOURCE_HEIGHT 0x26C 123 #define HI_TRANSPARENT_COLOR 0x270 124 #define V_DISPLAY_TEMP 0x274 /* No use */ 125 #define ALPHA_V3_FIFO_CONTROL 0x278 126 #define V3_SOURCE_WIDTH 0x27C 127 #define V3_COLOR_KEY 0x280 128 #define V1_ColorSpaceReg_1 0x284 129 #define V1_ColorSpaceReg_2 0x288 130 #define V1_STARTADDR_CB0 0x28C 131 #define V1_OPAQUE_CONTROL 0x290 /* To be deleted */ 132 #define V3_OPAQUE_CONTROL 0x294 /* To be deleted */ 133 #define V_COMPOSE_MODE 0x298 134 #define V3_STARTADDR_2 0x29C 135 #define V3_CONTROL 0x2A0 136 #define V3_STARTADDR_0 0x2A4 137 #define V3_STARTADDR_1 0x2A8 138 #define V3_STRIDE 0x2AC 139 #define V3_WIN_START_Y 0x2B0 140 #define V3_WIN_START_X 0x2B2 141 #define V3_WIN_END_Y 0x2B4 142 #define V3_WIN_END_X 0x2B6 143 #define V3_ALPHA_QWORD_PER_LINE 0x2B8 144 #define V3_ZOOM_CONTROL 0x2BC 145 #define V3_MINI_CONTROL 0x2C0 146 #define V3_ColorSpaceReg_1 0x2C4 147 #define V3_ColorSpaceReg_2 0x2C8 148 #define V3_DISPLAY_TEMP 0x2CC /* No use */ 149 #define V1_STARTADDR_CB1 0x2E4 150 #define V1_STARTADDR_CB2 0x2E8 151 #define V1_STARTADDR_CB3 0x2EC 152 #define V1_STARTADDR_CR0 0x2F0 153 #define V1_STARTADDR_CR1 0x2F4 154 #define V1_STARTADDR_CR2 0x2F8 155 #define V1_STARTADDR_CR3 0x2FC 156 /*CN400 and older Hardware Icon engine register*/ 157 #define HI_POSSTART 0x208 158 #define HI_CENTEROFFSET 0x20C 159 #define HI_FBOFFSET 0x224 160 #define HI_CONTROL 0x260 161 #define HI_TRANSPARENT_COLOR 0x270 162 #define HI_INVTCOLOR 0x274 163 /* VT3324 primary Hardware Icon engine register */ 164 #define PRIM_HI_POSEND 0x290 165 #define V327_HI_INVTCOLOR 0x2E4 166 #define PRIM_HI_FIFO 0x2E8 167 #define PRIM_HI_TRANSCOLOR 0x2EC 168 #define PRIM_HI_CTRL 0x2F0 169 #define PRIM_HI_FBOFFSET 0x2F4 170 #define PRIM_HI_POSSTART 0x2F8 171 #define PRIM_HI_CENTEROFFSET 0x2FC 172 #define PRIM_HI_INVTCOLOR 0x120C 173 174 /* Video Capture Engine Registers 175 * Capture Port 1 176 */ 177 #define CAP0_MASKS 0x100 178 #define CAP1_MASKS 0x104 179 #define CAP0_CONTROL 0x110 180 #define CAP0_H_RANGE 0x114 181 #define CAP0_V_RANGE 0x118 182 #define CAP0_SCAL_CONTROL 0x11C 183 #define CAP0_VBI_H_RANGE 0x120 184 #define CAP0_VBI_V_RANGE 0x124 185 #define CAP0_VBI_STARTADDR 0x128 186 #define CAP0_VBI_STRIDE 0x12C 187 #define CAP0_ANCIL_COUNT 0x130 188 #define CAP0_MAXCOUNT 0x134 189 #define CAP0_VBIMAX_COUNT 0x138 190 #define CAP0_DATA_COUNT 0x13C 191 #define CAP0_FB_STARTADDR0 0x140 192 #define CAP0_FB_STARTADDR1 0x144 193 #define CAP0_FB_STARTADDR2 0x148 194 #define CAP0_STRIDE 0x150 195 /* Capture Port 2 */ 196 #define CAP1_CONTROL 0x154 197 #define CAP1_SCAL_CONTROL 0x160 198 #define CAP1_VBI_H_RANGE 0x164 /*To be deleted*/ 199 #define CAP1_VBI_V_RANGE 0x168 /*To be deleted*/ 200 #define CAP1_VBI_STARTADDR 0x16C /*To be deleted*/ 201 #define CAP1_VBI_STRIDE 0x170 /*To be deleted*/ 202 #define CAP1_ANCIL_COUNT 0x174 /*To be deleted*/ 203 #define CAP1_MAXCOUNT 0x178 204 #define CAP1_VBIMAX_COUNT 0x17C /*To be deleted*/ 205 #define CAP1_DATA_COUNT 0x180 206 #define CAP1_FB_STARTADDR0 0x184 207 #define CAP1_FB_STARTADDR1 0x188 208 #define CAP1_STRIDE 0x18C 209 210 /* SUBPICTURE Registers */ 211 #define SUBP_CONTROL_STRIDE 0x3C0 212 #define SUBP_STARTADDR 0x3C4 213 #define RAM_TABLE_CONTROL 0x3C8 214 #define RAM_TABLE_READ 0x3CC 215 216 /* HQV Registers*/ 217 #define HQV_CONTROL 0x3D0 218 #define HQV_SRC_STARTADDR_Y 0x3D4 219 #define HQV_SRC_STARTADDR_U 0x3D8 220 #define HQV_SRC_STARTADDR_V 0x3DC 221 #define HQV_SRC_FETCH_LINE 0x3E0 222 #define HQV_FILTER_CONTROL 0x3E4 223 #define HQV_MINIFY_CONTROL 0x3E8 224 #define HQV_DST_STARTADDR0 0x3EC 225 #define HQV_DST_STARTADDR1 0x3F0 226 #define HQV_DST_STARTADDR2 0x3FC 227 #define HQV_DST_STRIDE 0x3F4 228 #define HQV_SRC_STRIDE 0x3F8 229 230 #define HQV_H_SCALE_CONTROL 0x3B0 231 #define HQV_V_SCALE_CONTROL 0x3B4 232 233 #define PRO_HQV1_OFFSET 0x1000 234 /* 235 * Video command definition 236 */ 237 /* #define V_ALPHA_CONTROL 0x210 */ 238 #define ALPHA_WIN_EXPIRENUMBER_4 0x00040000 239 #define ALPHA_WIN_CONSTANT_FACTOR_4 0x00004000 240 #define ALPHA_WIN_CONSTANT_FACTOR_12 0x0000c000 241 #define ALPHA_WIN_BLENDING_CONSTANT 0x00000000 242 #define ALPHA_WIN_BLENDING_ALPHA 0x00000001 243 #define ALPHA_WIN_BLENDING_GRAPHIC 0x00000002 244 #define ALPHA_WIN_PREFIFO_THRESHOLD_12 0x000c0000 245 #define ALPHA_WIN_FIFO_THRESHOLD_8 0x000c0000 246 #define ALPHA_WIN_FIFO_DEPTH_16 0x00100000 247 248 /* V_CHROMAKEY_LOW 0x228 */ 249 #define V_CHROMAKEY_V3 0x80000000 250 251 /* V1_CONTROL 0x230 */ 252 #define V1_ENABLE 0x00000001 253 #define V1_FULL_SCREEN 0x00000002 254 #define V1_YUV422 0x00000000 255 #define V1_RGB32 0x00000004 256 #define V1_RGB15 0x00000008 257 #define V1_RGB16 0x0000000C 258 #define V1_YCbCr420 0x00000010 259 #define V1_COLORSPACE_SIGN 0x00000080 260 #define V1_SRC_IS_FIELD_PIC 0x00000200 261 #define V1_SRC_IS_FRAME_PIC 0x00000000 262 #define V1_BOB_ENABLE 0x00400000 263 #define V1_FIELD_BASE 0x00000000 264 #define V1_FRAME_BASE 0x01000000 265 #define V1_SWAP_SW 0x00000000 266 #define V1_SWAP_HW_HQV 0x02000000 267 #define V1_SWAP_HW_CAPTURE 0x04000000 268 #define V1_SWAP_HW_MC 0x06000000 269 /* #define V1_DOUBLE_BUFFERS 0x00000000 */ 270 /* #define V1_QUADRUPLE_BUFFERS 0x18000000 */ 271 #define V1_EXPIRE_NUM 0x00050000 272 #define V1_EXPIRE_NUM_A 0x000a0000 273 #define V1_EXPIRE_NUM_F 0x000f0000 /* jason */ 274 #define V1_FIFO_EXTENDED 0x00200000 275 #define V1_ON_PRI 0x00000000 276 #define V1_ON_SND_DISPLAY 0x80000000 277 #define V1_FIFO_32V1_32V2 0x00000000 278 #define V1_FIFO_48V1_32V2 0x00200000 279 #define V1_PREFETCH_ON_3336 0x40000000 /*V1_PREFETCH_ON*/ 280 #define V1_GAMMA_ENABLE_3336 0x20000000 /*V1_Gamma_ENABLE*/ 281 282 /* V12_QWORD_PER_LINE 0x234 */ 283 #define V1_FETCH_COUNT 0x3ff00000 284 #define V1_FETCHCOUNT_ALIGNMENT 0x0000000f 285 #define V1_FETCHCOUNT_UNIT 0x00000004 /* Doubld QWORD */ 286 287 /* V1_STRIDE */ 288 #define V1_STRIDE_YMASK 0x00001fff 289 #define V1_STRIDE_UVMASK 0x1ff00000 290 291 /* V1_ZOOM_CONTROL 0x24C */ 292 #define V1_X_ZOOM_ENABLE 0x80000000 293 #define V1_Y_ZOOM_ENABLE 0x00008000 294 295 /* V1_MINI_CONTROL 0x250 */ 296 #define V1_X_INTERPOLY 0x00000002 /* X interpolation */ 297 #define V1_Y_INTERPOLY 0x00000001 /* Y interpolation */ 298 #define V1_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ 299 #define V1_X_DIV_2 0x01000000 300 #define V1_X_DIV_4 0x03000000 301 #define V1_X_DIV_8 0x05000000 302 #define V1_X_DIV_16 0x07000000 303 #define V1_Y_DIV_2 0x00010000 304 #define V1_Y_DIV_4 0x00030000 305 #define V1_Y_DIV_8 0x00050000 306 #define V1_Y_DIV_16 0x00070000 307 308 /* V1_STARTADDR0 0x254 */ 309 #define SW_FLIP_ODD 0x08000000 310 311 /* V_FIFO_CONTROL 0x258 312 * IA2 has 32 level FIFO for packet mode video format 313 * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable 314 * 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable 315 * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 316 */ 317 #define V1_FIFO_DEPTH12 0x0000000B 318 #define V1_FIFO_DEPTH16 0x0000000F 319 #define V1_FIFO_DEPTH32 0x0000001F 320 #define V1_FIFO_DEPTH48 0x0000002F 321 #define V1_FIFO_DEPTH64 0x0000003F 322 #define V1_FIFO_THRESHOLD6 0x00000600 323 #define V1_FIFO_THRESHOLD8 0x00000800 324 #define V1_FIFO_THRESHOLD12 0x00000C00 325 #define V1_FIFO_THRESHOLD16 0x00001000 326 #define V1_FIFO_THRESHOLD24 0x00001800 327 #define V1_FIFO_THRESHOLD32 0x00002000 328 #define V1_FIFO_THRESHOLD40 0x00002800 329 #define V1_FIFO_THRESHOLD48 0x00003000 330 #define V1_FIFO_THRESHOLD56 0x00003800 331 #define V1_FIFO_THRESHOLD61 0x00003D00 332 #define V1_FIFO_PRETHRESHOLD10 0x0A000000 333 #define V1_FIFO_PRETHRESHOLD12 0x0C000000 334 #define V1_FIFO_PRETHRESHOLD29 0x1d000000 335 #define V1_FIFO_PRETHRESHOLD40 0x28000000 336 #define V1_FIFO_PRETHRESHOLD44 0x2c000000 337 #define V1_FIFO_PRETHRESHOLD56 0x38000000 338 #define V1_FIFO_PRETHRESHOLD61 0x3D000000 339 340 #define VIDEO_FIFO_DEPTH_VT3336 225 341 #define VIDEO_FIFO_THRESHOLD_VT3336 200 342 #define VIDEO_FIFO_PRETHRESHOLD_VT3336 250 343 #define VIDEO_EXPIRE_NUM_VT3336 31 344 345 /* Those values are only valid for IGA1 */ 346 #define VIDEO_FIFO_DEPTH_VT3409 400 347 #define VIDEO_FIFO_THRESHOLD_VT3409 320 348 #define VIDEO_FIFO_PRETHRESHOLD_VT3409 230 349 #define VIDEO_EXPIRE_NUM_VT3409 160 350 351 /* ALPHA_V3_FIFO_CONTROL 0x278 352 * IA2 has 32 level FIFO for packet mode video format 353 * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable 354 * 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable 355 * 8 level FIFO for ALPHA 356 * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 357 */ 358 #define V3_FIFO_DEPTH16 0x0000000F 359 #define V3_FIFO_DEPTH24 0x00000017 360 #define V3_FIFO_DEPTH32 0x0000001F 361 #define V3_FIFO_DEPTH48 0x0000002F 362 #define V3_FIFO_DEPTH64 0x0000003F 363 #define V3_FIFO_THRESHOLD8 0x00000800 364 #define V3_FIFO_THRESHOLD12 0x00000C00 365 #define V3_FIFO_THRESHOLD16 0x00001000 366 #define V3_FIFO_THRESHOLD24 0x00001800 367 #define V3_FIFO_THRESHOLD29 0x00001D00 368 #define V3_FIFO_THRESHOLD32 0x00002000 369 #define V3_FIFO_THRESHOLD40 0x00002800 370 #define V3_FIFO_THRESHOLD48 0x00003000 371 #define V3_FIFO_THRESHOLD56 0x00003800 372 #define V3_FIFO_THRESHOLD61 0x00003D00 373 #define V3_FIFO_PRETHRESHOLD10 0x0000000A 374 #define V3_FIFO_PRETHRESHOLD12 0x0000000C 375 #define V3_FIFO_PRETHRESHOLD29 0x0000001d 376 #define V3_FIFO_PRETHRESHOLD40 0x00000028 377 #define V3_FIFO_PRETHRESHOLD44 0x0000002c 378 #define V3_FIFO_PRETHRESHOLD56 0x00000038 379 #define V3_FIFO_PRETHRESHOLD61 0x0000003D 380 #define V3_FIFO_MASK 0x0000007F 381 #define V3_FIFO_MASK_3314 0x000000FF 382 #define ALPHA_FIFO_DEPTH8 0x00070000 383 #define ALPHA_FIFO_THRESHOLD4 0x04000000 384 #define ALPHA_FIFO_MASK 0xffff0000 385 #define ALPHA_FIFO_PRETHRESHOLD4 0x00040000 386 387 /* IA2 */ 388 #define ColorSpaceValue_1 0x140020f2 389 #define ColorSpaceValue_2 0x0a0a2c00 390 391 #define ColorSpaceValue_1_3123C0 0x13000DED 392 #define ColorSpaceValue_2_3123C0 0x13171000 393 #define ColorSpaceValue_1_32045 0x13000DED 394 #define ColorSpaceValue_2_32045 0x13171000 395 396 /* For TV setting */ 397 #define ColorSpaceValue_1TV 0x140020f2 398 #define ColorSpaceValue_2TV 0x0a0a2c00 399 400 /* V_COMPOSE_MODE 0x298 */ 401 #define SELECT_VIDEO_IF_COLOR_KEY 0x00000001 /* select video if (color key),otherwise select graphics */ 402 #define SELECT_VIDEO3_IF_COLOR_KEY 0x00000020 /* For 3123C0, select video3 if (color key),otherwise select graphics */ 403 #define SELECT_VIDEO_IF_CHROMA_KEY 0x00000002 /* 0x0000000a //select video if (chroma key ),otherwise select graphics */ 404 #define ALWAYS_SELECT_VIDEO 0x00000000 /* always select video,Chroma key and Color key disable */ 405 #define COMPOSE_V1_V3 0x00000000 /* V1 on top of V3 */ 406 #define COMPOSE_V3_V1 0x00100000 /* V3 on top of V1 */ 407 #define COMPOSE_V1_TOP 0x00000000 408 #define COMPOSE_V3_TOP 0x00100000 409 #define V1_COMMAND_FIRE 0x80000000 /* V1 commands fire */ 410 #define V3_COMMAND_FIRE 0x40000000 /* V3 commands fire */ 411 #define V_COMMAND_LOAD 0x20000000 /* Video register always loaded */ 412 #define V_COMMAND_LOAD_VBI 0x10000000 /* Video register always loaded at vbi without waiting source flip */ 413 #define V3_COMMAND_LOAD 0x08000000 /* CLE_C0 Video3 register always loaded */ 414 #define V3_COMMAND_LOAD_VBI 0x00000100 /* CLE_C0 Video3 register always loaded at vbi without waiting source flip */ 415 #define SECOND_DISPLAY_COLOR_KEY_ENABLE 0x00010000 416 417 /* V3_ZOOM_CONTROL 0x2bc */ 418 #define V3_X_ZOOM_ENABLE 0x80000000 419 #define V3_Y_ZOOM_ENABLE 0x00008000 420 421 /* V3_MINI_CONTROL 0x2c0 */ 422 #define V3_X_INTERPOLY 0x00000002 /* X interpolation */ 423 #define V3_Y_INTERPOLY 0x00000001 /* Y interpolation */ 424 #define V3_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ 425 #define V3_X_DIV_2 0x01000000 426 #define V3_X_DIV_4 0x03000000 427 #define V3_X_DIV_8 0x05000000 428 #define V3_X_DIV_16 0x07000000 429 #define V3_Y_DIV_2 0x00010000 430 #define V3_Y_DIV_4 0x00030000 431 #define V3_Y_DIV_8 0x00050000 432 #define V3_Y_DIV_16 0x00070000 433 434 /* SUBP_CONTROL_STRIDE 0x3c0 */ 435 #define SUBP_HQV_ENABLE 0x00010000 436 #define SUBP_IA44 0x00020000 437 #define SUBP_AI44 0x00000000 438 #define SUBP_STRIDE_MASK 0x00001fff 439 #define SUBP_CONTROL_MASK 0x00070000 440 441 /* RAM_TABLE_CONTROL 0x3c8 */ 442 #define RAM_TABLE_RGB_ENABLE 0x00000007 443 444 /* CAPTURE0_CONTROL 0x310 */ 445 #define C0_ENABLE 0x00000001 446 #define BUFFER_2_MODE 0x00000000 447 #define BUFFER_3_MODE 0x00000004 448 #define BUFFER_4_MODE 0x00000006 449 #define SWAP_YUYV 0x00000000 450 #define SWAP_UYVY 0x00000100 451 #define SWAP_YVYU 0x00000200 452 #define SWAP_VYUY 0x00000300 453 #define IN_601_8 0x00000000 454 #define IN_656_8 0x00000010 455 #define IN_601_16 0x00000020 456 #define IN_656_16 0x00000030 457 #define DEINTER_ODD 0x00000000 458 #define DEINTER_EVEN 0x00001000 459 #define DEINTER_ODD_EVEN 0x00002000 460 #define DEINTER_FRAME 0x00003000 461 #define VIP_1 0x00000000 462 #define VIP_2 0x00000400 463 #define H_FILTER_2 0x00010000 464 #define H_FILTER_4 0x00020000 465 #define H_FILTER_8_1331 0x00030000 466 #define H_FILTER_8_12221 0x00040000 467 #define VIP_ENABLE 0x00000008 468 #define EN_FIELD_SIG 0x00000800 469 #define VREF_INVERT 0x00100000 470 #define FIELD_INPUT_INVERSE 0x00400000 471 #define FIELD_INVERSE 0x40000000 472 473 #define C1_H_MINI_EN 0x00000800 474 #define C0_H_MINI_EN 0x00000800 475 #define C1_V_MINI_EN 0x04000000 476 #define C0_V_MINI_EN 0x04000000 477 #define C1_H_MINI_2 0x00000400 478 479 /* CAPTURE1_CONTROL 0x354 */ 480 #define C1_ENABLE 0x00000001 481 482 /* V3_CONTROL 0x2A0 */ 483 #define V3_ENABLE 0x00000001 484 #define V3_FULL_SCREEN 0x00000002 485 #define V3_YUV422 0x00000000 486 #define V3_RGB32 0x00000004 487 #define V3_RGB15 0x00000008 488 #define V3_RGB16 0x0000000C 489 #define V3_COLORSPACE_SIGN 0x00000080 490 #define V3_EXPIRE_NUM 0x00040000 491 #define V3_EXPIRE_NUM_F 0x000f0000 492 #define V3_EXPIRE_NUM_3204 0x00100000 493 #define V3_EXPIRE_NUM_3205 0x00080000 494 #define V3_BOB_ENABLE 0x00400000 495 #define V3_FIELD_BASE 0x00000000 496 #define V3_FRAME_BASE 0x01000000 497 #define V3_SWAP_SW 0x00000000 498 #define V3_SWAP_HW_HQV 0x02000000 499 #define V3_FLIP_HW_CAPTURE0 0x04000000 500 #define V3_FLIP_HW_CAPTURE1 0x06000000 501 502 /* V3_ALPHA_FETCH_COUNT 0x2B8 */ 503 #define V3_FETCH_COUNT 0x3ff00000 504 #define ALPHA_FETCH_COUNT 0x000003ff 505 506 /* HQV_CONTROL 0x3D0 */ 507 #define HQV_RGB32 0x00000000 508 #define HQV_RGB16 0x20000000 509 #define HQV_RGB15 0x30000000 510 #define HQV_YUV422 0x80000000 511 #define HQV_YUV420 0xC0000000 512 #define HQV_ENABLE 0x08000000 513 #define HQV_SRC_SW 0x00000000 514 #define HQV_SRC_MC 0x01000000 515 #define HQV_SRC_CAPTURE0 0x02000000 516 #define HQV_SRC_CAPTURE1 0x03000000 517 #define HQV_FLIP_EVEN 0x00000000 518 #define HQV_FLIP_ODD 0x00000020 519 #define HQV_SW_FLIP 0x00000010 /* Write 1 to flip HQV buffer */ 520 #define HQV_DEINTERLACE 0x00010000 /* First line of odd field will be repeated 3 times */ 521 #define HQV_FIELD_2_FRAME 0x00020000 /* Src is field. Display each line 2 times */ 522 #define HQV_FRAME_2_FIELD 0x00040000 /* Src is field. Display field */ 523 #define HQV_FRAME_UV 0x00000000 /* Src is Non-interleaved */ 524 #define HQV_FIELD_UV 0x00100000 /* Src is interleaved */ 525 #define HQV_IDLE 0x00000008 526 #define HQV_FLIP_STATUS 0x00000001 527 #define HQV_DOUBLE_BUFF 0x00000000 528 #define HQV_TRIPLE_BUFF 0x04000000 529 #define HQV_SUBPIC_FLIP 0x00008000 530 #define HQV_FIFO_STATUS 0x00001000 531 #define HQV_GEN_IRQ 0x00000080 532 #define HQV_FIFO_DEPTH_1 0x00010000 533 /* for CME engine */ 534 #define HQV_SW_FLIP_QUEUE_ENABLE 0x00100000 535 536 /* for hwDiff->dwNewScaleCtl */ 537 #define HQV_H_SCALE_ENABLE 0x80000000 538 #define HQV_H_SCALE_UP 0x00000000 539 #define HQV_H_SCALE_DOWN_FOURTH_TO_1 0x10000000 540 #define HQV_H_SCALE_DOWN_FOURTH_TO_EIGHTH 0x20000000 541 #define HQV_H_SCALE_DOWN_UNDER_EIGHTH 0x30000000 542 543 #define HQV_V_SCALE_ENABLE 0x80000000 544 #define HQV_V_SCALE_UP 0x00000000 545 #define HQV_V_SCALE_DOWN 0x10000000 546 547 /* HQV Default Vodeo Color 0x3B8 */ 548 #define HQV_FIX_COLOR 0x0643212c 549 550 /* HQV_FILTER_CONTROL 0x3E4 */ 551 #define HQV_H_LOWPASS_2TAP 0x00000001 552 #define HQV_H_LOWPASS_4TAP 0x00000002 553 #define HQV_H_LOWPASS_8TAP1 0x00000003 /* To be deleted */ 554 #define HQV_H_LOWPASS_8TAP2 0x00000004 /* To be deleted */ 555 #define HQV_H_HIGH_PASS 0x00000008 556 #define HQV_H_LOW_PASS 0x00000000 557 #define HQV_V_LOWPASS_2TAP 0x00010000 558 #define HQV_V_LOWPASS_4TAP 0x00020000 559 #define HQV_V_LOWPASS_8TAP1 0x00030000 560 #define HQV_V_LOWPASS_8TAP2 0x00040000 561 #define HQV_V_HIGH_PASS 0x00080000 562 #define HQV_V_LOW_PASS 0x00000000 563 #define HQV_H_HIPASS_F1_DEFAULT 0x00000040 564 #define HQV_H_HIPASS_F2_DEFAULT 0x00000000 565 #define HQV_V_HIPASS_F1_DEFAULT 0x00400000 566 #define HQV_V_HIPASS_F2_DEFAULT 0x00000000 567 #define HQV_H_HIPASS_F1_2TAP 0x00000050 568 #define HQV_H_HIPASS_F2_2TAP 0x00000100 569 #define HQV_V_HIPASS_F1_2TAP 0x00500000 570 #define HQV_V_HIPASS_F2_2TAP 0x01000000 571 #define HQV_H_HIPASS_F1_4TAP 0x00000060 572 #define HQV_H_HIPASS_F2_4TAP 0x00000200 573 #define HQV_V_HIPASS_F1_4TAP 0x00600000 574 #define HQV_V_HIPASS_F2_4TAP 0x02000000 575 #define HQV_H_HIPASS_F1_8TAP 0x00000080 576 #define HQV_H_HIPASS_F2_8TAP 0x00000400 577 #define HQV_V_HIPASS_F1_8TAP 0x00800000 578 #define HQV_V_HIPASS_F2_8TAP 0x04000000 579 /* IA2 NEW */ 580 #define HQV_V_FILTER2 0x00080000 581 #define HQV_H_FILTER2 0x00000008 582 #define HQV_H_TAP2_11 0x00000041 583 #define HQV_H_TAP4_121 0x00000042 584 #define HQV_H_TAP4_1111 0x00000401 585 #define HQV_H_TAP8_1331 0x00000221 586 #define HQV_H_TAP8_12221 0x00000402 587 #define HQV_H_TAP16_1991 0x00000159 588 #define HQV_H_TAP16_141041 0x0000026A 589 #define HQV_H_TAP32 0x0000015A 590 #define HQV_V_TAP2_11 0x00410000 591 #define HQV_V_TAP4_121 0x00420000 592 #define HQV_V_TAP4_1111 0x04010000 593 #define HQV_V_TAP8_1331 0x02210000 594 #define HQV_V_TAP8_12221 0x04020000 595 #define HQV_V_TAP16_1991 0x01590000 596 #define HQV_V_TAP16_141041 0x026A0000 597 #define HQV_V_TAP32 0x015A0000 598 #define HQV_V_FILTER_DEFAULT 0x00420000 599 #define HQV_H_FILTER_DEFAULT 0x00000040 600 601 /* HQV_MINI_CONTROL 0x3E8 */ 602 #define HQV_H_MINIFY_ENABLE 0x00000800 603 #define HQV_H_MINIFY_DOWN 0x00001000 604 #define HQV_V_MINIFY_ENABLE 0x08000000 605 #define HQV_V_MINIFY_DOWN 0x10000000 606 #define HQV_VDEBLOCK_FILTER 0x80000000 607 #define HQV_HDEBLOCK_FILTER 0x00008000 608 609 /* new added registers for VT3409.For some registers have different meanings 610 * but the same address,we add postfix _409 to distinguish */ 611 #define HQV_COLOR_ADJUSTMENT_PRE_CTRL1 0x360 612 #define HQV_COLOR_ADJUSTMENT_PRE_CTRL2 0x364 613 #define HQV_COLOR_ADJUSTMENT_PRE_CTRL3 0x368 614 #define HQV_COLOR_ADJUSTMENT_PRE_CTRL4 0x36C 615 #define HQV_SRC_DATA_OFFSET_CTRL1_409 0x370 616 #define HQV_SRC_DATA_OFFSET_CTRL2_409 0x374 617 #define HQV_SRC_DATA_OFFSET_CTRL3_409 0x378 618 #define HQV_SRC_DATA_OFFSET_CTRL4_409 0x37C 619 #define HQV_DST_DATA_OFFSET_CTRL1 0x380 620 #define HQV_DST_DATA_OFFSET_CTRL2 0x384 621 #define HQV_DST_DATA_OFFSET_CTRL3 0x388 622 #define HQV_DST_DATA_OFFSET_CTRL4 0x38C 623 #define HQV_SHARPNESS_DECODER_HANDSHAKE_CTRL_410 0x3A4 624 #define HQV_RESIDUE_PIXEL_FRAME_STARTADDR 0x3BC 625 #define HQV_BACKGROUND_DATA_OFFSET 0x3CC 626 #define HQV_SUBP_HSCALE_CTRL 0x3E0 627 #define HQV_SUBP_VSCALE_CTRL 0x3E8 628 629 /* Add new HQV Registers for VT3353: */ 630 #define HQV_SRC_DATA_OFFSET_CONTROL1 0x380 631 #define HQV_SRC_DATA_OFFSET_CONTROL2 0x384 632 #define HQV_SRC_DATA_OFFSET_CONTROL3 0x388 633 #define HQV_SRC_DATA_OFFSET_CONTROL4 0x38C 634 #define HQV_HW_TUNING_PERFORMANCE 0x390 635 #define HQV_EXTENDED_CONTROL 0x394 636 #define HQV_STATIC_RECORD_FB_STARTADDR 0x398 637 #define HQV_STATIC_RECORD_FB_STRIDE 0x39C 638 #define HQV_COLOR_ADJUSTMENT_CONTROL1 0x3A0 639 #define HQV_COLOR_ADJUSTMENT_CONTROL2 0x3A4 640 #define HQV_COLOR_ADJUSTMENT_CONTROL3 0x3A8 641 #define HQV_COLOR_ADJUSTMENT_CONTROL5 0x3AC 642 #define HQV_DEFAULT_VIDEO_COLOR 0x3B8 643 644 #define CHROMA_KEY_LOW 0x00FFFFFF 645 #define CHROMA_KEY_HIGH 0x00FFFFFF 646 647 /* V_CAP_STATUS */ 648 #define V_ST_UPDATE_NOT_YET 0x00000003 649 #define V1_ST_UPDATE_NOT_YET 0x00000001 650 #define V3_ST_UPDATE_NOT_YET 0x00000008 651 652 #define VBI_STATUS 0x00000002 653 654 /* 655 * Macros for Video MMIO 656 */ 657 #ifndef V4L2 658 #define MPGOutD(port, data) *((volatile CARD32 *)(pVia->MpegMapBase +(port))) = (data) 659 #define MPGInD(port) *((volatile CARD32 *)(pVia->MpegMapBase +(port))) 660 #endif 661 662 /* 663 * Macros for GE MMIO 664 */ 665 #define GEInW(port) *((volatile CARD16 *)(lpGEMMIO + (port))) 666 #define GEInD(port) *((volatile CARD32 *)(lpGEMMIO + (port))) 667 #define GEOutW(port, data) *((volatile CARD16 *)(lpGEMMIO + (port))) = (data) 668 #define GEOutD(port, data) *((volatile CARD32 *)(lpGEMMIO + (port))) = (data) 669 670 /* 671 * MPEG 1/2 Slice Engine (at 0xC00 relative to base) 672 */ 673 674 #define MPG_CONTROL 0x00 675 #define MPG_CONTROL_STRUCT 0x03 676 #define MPG_CONTROL_STRUCT_TOP 0x01 677 #define MPG_CONTROL_STRUCT_BOTTOM 0x02 678 #define MPG_CONTROL_STRUCT_FRAME 0x03 679 /* Use TOP if interlaced */ 680 #define MPG_CONTROL_TYPE 0x3C 681 #define MPG_CONTROL_TYPE_I (0x01 << 2) 682 #define MPG_CONTROL_TYPE_B (0x02 << 2) 683 #define MPG_CONTROL_TYPE_P (0x03 << 3) 684 #define MPG_CONTROL_ALTSCAN 0x40 685 #define MPG_BLOCK 0x08 /* Unsure */ 686 #define MPG_COMMAND 0x0C 687 #define MPG_DATA1 0x10 688 #define MPG_DATA2 0x14 689 #define MPG_DATA3 0x18 690 #define MPG_DATA4 0x1C 691 692 #define MPG_YPHYSICAL(x) (0x20 + 12*(x)) 693 #define MPG_CbPHYSICAL(x) (0x24 + 12*(x)) 694 #define MPG_CrPHYSICAL(x) (0x28 + 12*(x)) 695 696 #define MPG_PITCH 0x50 697 #define MPG_STATUS 0x54 698 699 #define MPG_MATRIX_IDX 0x5C 700 #define MPG_MATRIX_IDX_INTRA 0x00 701 #define MPG_MATRIX_IDX_NON 0x01 702 #define MPG_MATRIX_DATA 0x60 703 704 #define MPG_SLICE_CTRL_1 0x90 705 #define MPG_SLICE_MBAMAX 0x2FFF 706 #define MPG_SLICE_PREDICTIVE_DCT 0x4000 707 #define MPG_SLICE_TOP_FIRST 0x8000 708 #define MPG_SLICE_MACROBLOCK_WIDTH(x) ((x)<<18) /* in 64's */ 709 #define MPG_SLICE_CTRL_2 0x94 710 #define MPG_SLICE_CONCEAL_MVEC 0x0000001 711 #define MPG_SLICE_QSCALE_TYPE 0x0000002 712 #define MPG_SLICE_DCPRECISION 0x000000C 713 #define MPG_SLICE_MACROBQUOT 0x0FFFFF0 714 #define MPG_SLICE_INTRAVLC 0x1000000 715 #define MPG_SLICE_CTRL_3 0x98 716 #define MPG_SLICE_FHMVR 0x0000003 717 #define MPG_SLICE_FVMVR 0x000000C 718 #define MPG_SLICE_BHMVR 0x0000030 719 #define MPG_SLICE_BVMVR 0x00000C0 720 #define MPG_SLICE_SECOND_FIELD 0x0100000 721 #define MPG_SLICE_RESET 0x0400000 722 #define MPG_SLICE_LENGTH 0x9C 723 #define MPG_SLICE_DATA 0xA0 724 725 #ifdef HAVE_PCIACCESS 726 #define VIA_MEMBASE(p,n) (p)->regions[(n)].base_addr 727 #define VENDOR_ID(p) (p)->vendor_id 728 #define DEVICE_ID(p) (p)->device_id 729 #define SUBVENDOR_ID(p) (p)->subvendor_id 730 #define SUBSYS_ID(p) (p)->subdevice_id 731 #define CHIP_REVISION(p) (p)->revision 732 #else 733 #define VIA_MEMBASE(p,n) (p)->memBase[n] 734 #define VENDOR_ID(p) (p)->vendor 735 #define DEVICE_ID(p) (p)->chipType 736 #define SUBVENDOR_ID(p) (p)->subsysVendor 737 #define SUBSYS_ID(p) (p)->subsysCard 738 #define CHIP_REVISION(p) (p)->chipRev 739 #endif 740 741 #endif /* _VIA_ENG_REGS_H_ */ 742
Indexes created Mon Aug 10 00:24:53 UTC 2026