1 /* $NetBSD: vectors.h,v 1.6 2024/02/01 22:00:29 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _M68K_VECTORS_H_ 33 #define _M68K_VECTORS_H_ 34 35 /* 36 * Vector numbers (*4 for byte offset into table). 37 * 38 * VECI_RIISP and VECI_RIPC are fetched using Supervisor Program 39 * space. The rest, Supervisor Data space. 40 * 41 * VECI_PMMU_ILLOP and VECI_PMMU_ACCESS are defined for the 68020, but 42 * not used on the 68030. 43 * 44 * VECI_CPV and VECI_PMMU_CONF are defined for the 68020 and 68030, but 45 * not used on the 68040 or 68060. 46 * 47 * VECI_UNIMP_FP_DATA, VECI_UNIMP_EA and VECI_UNIMP_II are defined for 48 * the 68060 and reserved on all other processors. 49 */ 50 #define VECI_RIISP 0 /* Reset Initial Interrupt SP */ 51 #define VECI_RIPC 1 /* Reset Initial PC */ 52 #define VECI_BUSERR 2 /* Bus Error */ 53 #define VECI_ADDRERR 3 /* Address Error */ 54 #define VECI_ILLINST 4 /* Illegal Instruction */ 55 #define VECI_ZERODIV 5 /* Zero Divide */ 56 #define VECI_CHK 6 /* CHK, CHK2 instruction */ 57 #define VECI_TRAPcc 7 /* cpTRAPcc, TRAPcc, TRAPV */ 58 #define VECI_PRIV 8 /* Privilege Violation */ 59 #define VECI_TRACE 9 /* Trace */ 60 #define VECI_LINE1010 10 /* Line 1010 Emulator */ 61 #define VECI_LINE1111 11 /* Line 1111 Emulator */ 62 #define VECI_rsvd12 12 /* unassigned, reserved */ 63 #define VECI_CPV 13 /* Coprocessor Protocol Violation */ 64 #define VECI_FORMATERR 14 /* Format Error */ 65 #define VECI_UNINT_INTR 15 /* Uninitialized Interrupt */ 66 #define VECI_rsvd16 16 /* unassigned, reserved */ 67 #define VECI_rsvd17 17 /* unassigned, reserved */ 68 #define VECI_rsvd18 18 /* unassigned, reserved */ 69 #define VECI_rsvd19 19 /* unassigned, reserved */ 70 #define VECI_rsvd20 20 /* unassigned, reserved */ 71 #define VECI_rsvd21 21 /* unassigned, reserved */ 72 #define VECI_rsvd22 22 /* unassigned, reserved */ 73 #define VECI_rsvd23 23 /* unassigned, reserved */ 74 #define VECI_INTRAV0 24 /* Spurious Interrupt */ 75 #define VECI_SPURIOUS_INTR VECI_INTRAV0 76 #define VECI_INTRAV1 25 /* Level 1 Interrupt Autovector */ 77 #define VECI_INTRAV2 26 /* Level 2 Interrupt Autovector */ 78 #define VECI_INTRAV3 27 /* Level 3 Interrupt Autovector */ 79 #define VECI_INTRAV4 28 /* Level 4 Interrupt Autovector */ 80 #define VECI_INTRAV5 29 /* Level 5 Interrupt Autovector */ 81 #define VECI_INTRAV6 30 /* Level 6 Interrupt Autovector */ 82 #define VECI_INTRAV7 31 /* Level 7 Interrupt Autovector */ 83 #define VECI_TRAP0 32 /* Trap #0 instruction */ 84 #define VECI_TRAP1 33 /* Trap #1 instruction */ 85 #define VECI_TRAP2 34 /* Trap #2 instruction */ 86 #define VECI_TRAP3 35 /* Trap #3 instruction */ 87 #define VECI_TRAP4 36 /* Trap #4 instruction */ 88 #define VECI_TRAP5 37 /* Trap #5 instruction */ 89 #define VECI_TRAP6 38 /* Trap #6 instruction */ 90 #define VECI_TRAP7 39 /* Trap #7 instruction */ 91 #define VECI_TRAP8 40 /* Trap #8 instruction */ 92 #define VECI_TRAP9 41 /* Trap #9 instruction */ 93 #define VECI_TRAP10 42 /* Trap #10 instruction */ 94 #define VECI_TRAP11 43 /* Trap #11 instruction */ 95 #define VECI_TRAP12 44 /* Trap #12 instruction */ 96 #define VECI_TRAP13 45 /* Trap #13 instruction */ 97 #define VECI_TRAP14 46 /* Trap #14 instruction */ 98 #define VECI_TRAP15 47 /* Trap #15 instruction */ 99 #define VECI_FP_BSUN 48 /* FPCP Branch or Set on Unordered */ 100 #define VECI_FP_INEX 49 /* FPCP Inexact Result */ 101 #define VECI_FP_DZ 50 /* FPCP Divide by Zero */ 102 #define VECI_FP_UNFL 51 /* FPCP Underflow */ 103 #define VECI_FP_OPERR 52 /* FPCP Operand Error */ 104 #define VECI_FP_OVFL 53 /* FPCP Overflow */ 105 #define VECI_FP_SNAN 54 /* FPCP Signalling NaN */ 106 #define VECI_UNIMP_FP_DATA 55 /* FP Unimplemented Data Type */ 107 #define VECI_PMMU_CONF 56 /* PMMU Configuration */ 108 #define VECI_PMMU_ILLOP 57 /* PMMU Illegal Operation */ 109 #define VECI_PMMU_ACCESS 58 /* PMMU Access Level Violation */ 110 #define VECI_rsvd59 59 /* unassigned, reserved */ 111 #define VECI_UNIMP_EA 60 /* Unimplemented Effective Address */ 112 #define VECI_UNIMP_II 61 /* Unimplemented Integer Instruction */ 113 #define VECI_rsvd62 62 /* unassigned, reserved */ 114 #define VECI_rsvd63 63 /* unassigned, reserved */ 115 #define VECI_USRVEC_START 64 /* User defined vectors (192) */ 116 117 #define NVECTORS 256 118 #define NAUTOVECTORS 8 119 #define NUSERVECTORS (NVECTORS - VECI_USRVEC_START) 120 121 #define VECI_INTRAV(ipl) ((ipl) + VECI_SPURIOUS_INTR) 122 #define VECI_TRAP(x) ((x) + VECI_TRAP0) 123 124 #define VECI_TO_VECO(x) ((x) << 2) 125 #define VECO_TO_VECI(x) ((uint8_t)((unsigned int)(x) >> 2)) 126 127 #ifdef _KERNEL 128 129 extern void *vectab[NVECTORS]; 130 extern void **saved_vbr; 131 132 void vec_init(void); 133 void vec_reset(void); 134 void *vec_get_entry(int); 135 void vec_set_entry(int, void *); 136 137 #endif /* _KERNEL */ 138 139 #endif /* _M68K_VECTORS_H_ */ 140
Indexes created Mon Sep 22 13:09:51 GMT 2025