1 /* $NetBSD: summitreg.h,v 1.20 2025/12/16 09:49:48 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2024 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* HP Visualize FX 4 and related hardware, aka Summit */ 30 31 /* 32 * register values, found by disassembling the ROM 33 * some found by Sven Schnelle 34 * ( see https://patchwork.kernel.org/project/linux-parisc/patch/20211031204952.25678-2-svens@stackframe.org/ ) 35 * some by me 36 */ 37 38 #ifndef SUMMITREG_H 39 #define SUMMITREG_H 40 41 #define VISFX_CONTROL 0x641000 42 #define CONTROL_WFC 0x00000200 // FIFO when 0, direct when 1 43 #define VISFX_FC 0x641040 // Fault Control 44 #define VISFX_STATUS 0x641400 // zero when idle 45 /* 46 * about the FIFO register: 47 * - on FX4, there are 0x800 FIFO slots, quite a lot 48 * - based on observation, every register write seems to occupy *two* slots 49 * - we need to write 0 to VISFX_CONTROL to enable FIFO pacing 50 * - the FIFO is quite difficult to overrun but things like x11perf copywinwin 51 * will do it if we're not careful 52 */ 53 #define VISFX_FIFO 0x641440 54 #define VISFX_FOEU 0x920400 // Fragment Operation Enable 55 #define VISFX_FOE 0x920404 // Fragment Operation Enable 56 #define FOE_TEXTURE 0x00000001 57 #define FOE_SPECULAR 0x00000002 58 #define FOE_DEPTHCUE 0x00000004 59 #define FOE_ALPHATEST 0x00000008 60 #define FOE_STENCIL 0x00000010 61 #define FOE_Z_TEST 0x00000020 62 #define FOE_BLEND_ROP 0x00000040 // IBO is used 63 #define FOE_DITHER 0x00000080 64 #define VISFX_RBS 0x920860 // STI writes 0xe4 into this on FX5 65 // seems to be another byte swapper 66 #define VISFX_IBO 0x921110 // ROP in lowest nibble 67 #define RopClr 0x0 68 #define RopSrc 0x3 69 #define RopInv 0xc 70 #define RopSet 0xf 71 72 #define VISFX_CBR 0x92111c // constant colour for blending 73 #define VISFX_IAA0 0x921200 // XLUT, 16 entries 74 #define VISFX_IAA(n) (0x921200 + ((n) << 2)) 75 #define VISFX_OTR 0x921148 // overlay transparency 76 77 #define VISFX_FCDA 0x9211d8 // FX5 zeroes this, 78 /* 79 0x00010000 - some sort of mask 80 0x00020000 and 0x00040000 - similar patterns, different colours 81 */ 82 83 #define B2_MBWB 0x921194 84 #define B2_MBWC 0x921198 85 #define B2_MBWD 0x92119c 86 87 #define VISFX_VRAM_WRITE_MODE 0xa00808 88 #define VISFX_VRAM_READ_MODE 0xa0080c 89 #define VISFX_PIXEL_MASK 0xa0082c 90 #define VISFX_FG_COLOUR 0xa0083c 91 #define VISFX_BG_COLOUR 0xa00844 92 #define VISFX_PLANE_MASK 0xa0084c 93 /* this controls what we see in the FB aperture */ 94 #define VISFX_APERTURE_ACCESS 0xa00858 95 #define VISFX_DEPTH_8 0x30 96 #define VISFX_DEPTH_32 0x50 97 #define VISFX_RPH 0xa0085c // read prefetch hint 98 #define VISFX_RPH_RTL 0x80000000 // right-to-left 99 #define VISFX_RPH_LTR 0x00000000 // left-to-right 100 101 #define B2_BMAP_DBA 0xa008a4 102 103 #define VISFX_READ_DATA 0xa41480 104 105 /* 106 * HP calls these BINC writes on NGLE 107 * basically, you set write mode, POE, IBO etc., poke your destination 108 * coordinates into VISFX_VRAM_WRITE_DEST, then write pixels into a DATA_* 109 * register, which will perform the programmed operation(s) and move the 110 * destination coordinates 111 */ 112 #define VISFX_VRAM_WRITE_DATA_INCRX 0xa60000 113 #define VISFX_VRAM_WRITE_DATA_INCRY 0xa68000 114 #define VISFX_VRAM_WRITE_DEST 0xac1000 115 116 #define VISFX_TCR 0xac1024 /* throttle control */ 117 #define VISFX_CLIP_TL 0xac1050 /* clipping rect, top/left */ 118 #define VISFX_CLIP_WH 0xac1054 /* clipping rect, w/h */ 119 120 #define VISFX_WRITE_MODE_PLAIN 0x02000000 121 #define VISFX_WRITE_MODE_EXPAND 0x050004c0 122 #define VISFX_WRITE_MODE_FILL 0x050008c0 123 #define VISFX_WRITE_MODE_TRANSPARENT 0x00000800 /* bg is tansparent */ 124 #define VISFX_WRITE_MODE_MASK 0x00000400 /* apply pixel mask */ 125 /* 0x00000200 - some pattern */ 126 /* looks like 0x000000c0 enables fg/bg colours to be applied */ 127 128 #define VISFX_READ_MODE_COPY 0x02000400 129 130 #define OTC01 0x00000000 /* one pixel per 32bit write */ 131 #define OTC04 0x02000000 /* 4 pixels per 32bit write */ 132 #define OTC32 0x05000000 /* 32 pixels per 32bit write */ 133 #define BIN8I 0x00000000 /* 8bit indexed */ 134 #define BIN12I 0x00010000 /* 12bit indexed */ 135 #define BIN332F 0x00040000 /* R3G3B2 */ 136 #define BIN8F 0x00070000 /* ARGB8 */ 137 #define BINapln 0x00110000 /* attribute plane */ 138 #define BINhost 0x00300000 /* DMA to host */ 139 #define BUFovl 0x00000000 /* 8bit overlay */ 140 #define BUFBL 0x00008000 /* back/left */ 141 #define BUFFL 0x00004000 /* front/left */ 142 #define BUFBR 0x00002000 /* back/right */ 143 #define BUFFR 0x00001000 /* front/right */ 144 145 /* attribute table, this only selects depth and CFS */ 146 #define IAA_8I 0x00000000 /* 8bit CI */ 147 #define IAA_8F 0x00000070 /* RGB8 */ 148 #define IAA_CFS0 0x00000000 /* CFS select */ 149 #define IAA_CFS1 0x00000100 /* CFS 1 etc. */ 150 151 /* overlay transparency register */ 152 #define OTR_T 0x00010000 /* when set 0 is transparent, otherwise 0xff */ 153 #define OTR_A 0x00000100 /* always transparent */ 154 #define OTR_L1 0x00000002 /* transparency controlled by CFS17 */ 155 #define OTR_L0 0x00000001 /* transparency controlled by CFS16 */ 156 157 /* 158 * for STI colour change mode: 159 * set VISFX_FG_COLOUR, VISFX_BG_COLOUR 160 * set VISFX_VRAM_READ_MODE 0x05000400 161 * set VISFX_VRAM_WRITE_MODE 0x050000c0 162 */ 163 164 /* fill */ 165 #define VISFX_START 0xb3c000 166 #define VISFX_SIZE 0xb3c808 /* start, FX4 uses 0xb3c908 */ 167 168 /* copy */ 169 #define VISFX_COPY_SRC 0xb3c010 170 #define VISFX_COPY_WH 0xb3c008 171 #define VISFX_COPY_DST 0xb3cc00 172 /* 173 * looks like ORing 0x800 to the register address starts a command 174 * - 0x800 - fill 175 * - 0xc00 - copy 176 * 0x100 and 0x200 seem to have functions as well, not sure what though 177 * for example, the FX4 ROM uses 0xb3c908 to start a rectangle fill, but 178 * it also works with 0xb3c808 and 0xb3ca08 179 * same with copy, 0xc00 seems to be what matters, setting 0x100 or 0x200 180 * doesn't seem to make a difference 181 * 0x400 or 0x100 by themselves don't start a command either 182 */ 183 184 /* 185 * alpha blending operations 186 * source and destination blend functions are in 0xf0 and 0x0f 187 * how they're combined is in 0x700 188 */ 189 #define IBO_ROP 0 /* ROP in lower 4 bit */ 190 #define IBO_ADD 0x200 191 #define IBO_S_MINUS_D 0x400 /* source - dest */ 192 #define IBO_D_MINUS_S 0x500 /* dest - source */ 193 #define IBO_MIN 0x600 194 #define IBO_MAX 0x700 195 196 /* 197 * here are the blend functions I identified 198 * apparently the upper byte in 32bit mode is not implemented on FX2/4/6, and 199 * neither is any blend mode that takes the colour value from CBR 200 * so no blending with screen-to-screen blits, alpha will always read zero 201 * the only ways to actually use alpha blending is with fills ( the alpha part 202 * of the FG register is used ) and BINC writes, or when using constant alpha 203 */ 204 #define IBO_ZERO 0 205 #define IBO_ONE 1 206 #define IBO_SRC 4 /* src alpha */ 207 #define IBO_ONE_MINUS_SRC 5 /* 1 - src alpha */ 208 #define IBO_CBR 14 /* alpha from CBR */ 209 #define IBO_ONE_MINUS_CBR 15 /* 1 - alpha from CBR */ 210 211 #define SRC(n) ((n) << 4) 212 #define DST(n) (n) 213 /* 214 * use unbuffered space for cursor registers 215 * The _POS, _INDEX and _DATA registers work exactly like on HCRX 216 */ 217 218 #define VISFX_CURSOR_POS 0x400000 219 #define VISFX_CURSOR_ENABLE 0x80000000 220 #define VISFX_CURSOR_INDEX 0x400004 221 #define VISFX_CURSOR_DATA 0x400008 222 #define VISFX_CURSOR_FG 0x40000c 223 #define VISFX_CURSOR_BG 0x400010 224 #define VISFX_COLOR_MASK 0x800018 225 #define VISFX_COLOR_INDEX 0x800020 226 #define VISFX_COLOR_VALUE 0x800024 227 #define VISFX_FATTR 0x80003c /* force attribute */ 228 #define VISFX_MPC 0x80004c 229 #define MPC_VIDEO_ON 0x0c 230 #define MPC_VSYNC_OFF 0x02 231 #define MPC_HSYNC_OFF 0x01 232 #define VISFX_CFS0 0x800100 /* colour function select */ 233 #define VISFX_CFS(n) (VISFX_CFS0 + ((n) << 2)) 234 /* 235 * 0 ... 6 for image planes, 7 or bypass, 16 and 17 for overlay 236 * these are selected by IAA* or FATTR registers 237 */ 238 #define CFS_CR 0x80 // enable color recovery 239 #define CFS_332 0x00 // R3G3B2 240 #define CFS_8I 0x40 // 8bit indexed 241 #define CFS_8F 0x70 // ARGB8 242 #define CFS_LUT0 0x00 // use LUT 0 243 #define CFS_LUT1 0x01 // LUT 1 etc. 244 #define CFS_BYPASS 0x07 // bypass LUT 245 246 /* FX5 byte swapping stuff */ 247 #define B2_DMA_BSCFB 0xaa0408 // byte swapping on buffered FB reads 248 #define UB_DMA_UBSCFB 0x6a0c08 // byte swapping on unbuffered FB reads 249 #define B2_PDU_BSCFB 0xa4303c // byte swapping on buffered FB writes 250 #define UB_PDU_UBSCFB 0x64303c // byte swapping on unbuffered FB writes 251 #define B2_MFU_BSCTD 0xb08044 // byte swapping on TD registers 252 #define B2_MFU_BSCCTL 0xb08048 // byte swapping on TD pair registers 253 #define B2_DMA_BSCBLK 0xaa0600 // blanket swapper, 0x01 enables swapping 254 #define B2_DMA_BSCSAV 0xaa0640 // blanket swapper with enable bits 255 256 #define SWAP_0123 0x1b1b1b1b // 0b00.01.10.11 -> 0x1b 257 #define SWAP_3210 0xe4e4e4e4 // 0b11.10.01.00 -> 0xe4 258 #endif /* SUMMITREG_H */ 259
Indexes created Sun Feb 22 16:20:20 UTC 2026