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      1 /* $NetBSD: meson_vpureg.h,v 1.1 2019/01/19 21:43:43 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _MESON_VPUREG_H
     30 #define _MESON_VPUREG_H
     31 
     32 #define VPU_REG(n)	((n) << 2)
     33 
     34 #define VIU_OSD2_CTRL_STAT_REG		VPU_REG(0x1a30)
     35 #define VIU_OSD2_TCOLOR_AG0_REG		VPU_REG(0x1a37)
     36 #define VIU_OSD2_TCOLOR_AG1_REG		VPU_REG(0x1a38)
     37 #define VIU_OSD2_TCOLOR_AG2_REG		VPU_REG(0x1a39)
     38 #define VIU_OSD2_TCOLOR_AG3_REG		VPU_REG(0x1a3a)
     39 #define VIU_OSD2_BLK0_CFG_W0_REG	VPU_REG(0x1a3b)
     40 #define VIU_OSD2_BLK0_CFG_W1_REG	VPU_REG(0x1a3c)
     41 #define VIU_OSD2_BLK0_CFG_W2_REG	VPU_REG(0x1a3d)
     42 #define VIU_OSD2_BLK0_CFG_W3_REG	VPU_REG(0x1a3e)
     43 #define VIU_OSD2_BLK0_CFG_W4_REG	VPU_REG(0x1a64)
     44 #define VPP_MISC_REG			VPU_REG(0x1d26)
     45 #define VPP_OSD_VSC_PHASE_STEP_REG	VPU_REG(0x1dc0)
     46 #define VPP_OSD_VSC_INI_PHASE_REG	VPU_REG(0x1dc1)
     47 #define VPP_OSD_VSC_CTRL0_REG		VPU_REG(0x1dc2)
     48 #define VPP_OSD_HSC_PHASE_STEP_REG	VPU_REG(0x1dc3)
     49 #define VPP_OSD_HSC_INI_PHASE_REG	VPU_REG(0x1dc4)
     50 #define VPP_OSD_HSC_CTRL0_REG		VPU_REG(0x1dc5)
     51 #define VPP_OSD_SC_DUMMY_DATA_REG	VPU_REG(0x1dc7)
     52 #define VPP_OSD_SC_CTRL0_REG		VPU_REG(0x1dc8)
     53 #define VPP_OSD_SCI_WH_M1_REG		VPU_REG(0x1dc9)
     54 #define VPP_OSD_SCO_H_REG		VPU_REG(0x1dca)
     55 #define VPP_OSD_SCO_V_REG		VPU_REG(0x1dcb)
     56 
     57 #define VIU_OSD_CTRL_STAT_ENABLE	__BIT(21)
     58 #define VIU_OSD_CTRL_STAT_GLOBAL_ALPHA	__BITS(20,12)
     59 #define VIU_OSD_CTRL_STAT_BLK3_ENABLE	__BIT(3)
     60 #define VIU_OSD_CTRL_STAT_BLK2_ENABLE	__BIT(2)
     61 #define VIU_OSD_CTRL_STAT_BLK1_ENABLE	__BIT(1)
     62 #define VIU_OSD_CTRL_STAT_BLK0_ENABLE	__BIT(0)
     63 
     64 #define VIU_OSD_TCOLOR_R		__BITS(31,24)
     65 #define VIU_OSD_TCOLOR_G		__BITS(23,16)
     66 #define VIU_OSD_TCOLOR_B		__BITS(15,8)
     67 #define VIU_OSD_TCOLOR_A		__BITS(7,0)
     68 
     69 #define VIU_OSD_BLK_CFG_W0_TBL_ADDR	__BITS(23,16)
     70 #define VIU_OSD_BLK_CFG_W0_LITTLE_ENDIAN __BIT(15)
     71 #define VIU_OSD_BLK_CFG_W0_RPT_Y	__BIT(14)
     72 #define VIU_OSD_BLK_CFG_W0_INTERP_CTRL	__BITS(13,12)
     73 #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE	__BITS(11,8)
     74 #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_PAL4	0
     75 #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_PAL16	1
     76 #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_PAL256	2
     77 #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_YUV	3
     78 #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_16BPP	4
     79 #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_32BPP	5
     80 #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_24BPP	7
     81 #define VIU_OSD_BLK_CFG_W0_RGB_EN	__BIT(7)
     82 #define VIU_OSD_BLK_CFG_W0_TC_ALPHA_EN	__BIT(6)
     83 #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX	__BITS(5,2)
     84 #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_RGB	0
     85 #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_RGBA	0
     86 #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_ARGB	1
     87 #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_ABGR	2
     88 #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_BGRA	3
     89 #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_RGB565	4
     90 #define VIU_OSD_BLK_CFG_W0_INTERLACE_EN	__BIT(1)
     91 #define VIU_OSD_BLK_CFG_W0_INTERLACE_SEL_ODD __BIT(0)
     92 
     93 #define VIU_OSD_BLK_CFG_W1_X_END	__BITS(28,16)
     94 #define VIU_OSD_BLK_CFG_W1_X_START	__BITS(12,0)
     95 
     96 #define VIU_OSD_BLK_CFG_W2_Y_END	__BITS(28,16)
     97 #define VIU_OSD_BLK_CFG_W2_Y_START	__BITS(12,0)
     98 
     99 #define VIU_OSD_BLK_CFG_W3_H_END	__BITS(27,16)
    100 #define VIU_OSD_BLK_CFG_W3_H_START	__BITS(11,0)
    101 
    102 #define VIU_OSD_BLK_CFG_W4_V_END	__BITS(27,16)
    103 #define VIU_OSD_BLK_CFG_W4_V_START	__BITS(11,0)
    104 
    105 #define VPP_MISC_OSD2_PREBLEND		__BIT(17)
    106 #define VPP_MISC_OSD1_PREBLEND		__BIT(16)
    107 #define VPP_MISC_OSD2_POSTBLEND		__BIT(13)
    108 #define VPP_MISC_OSD1_POSTBLEND		__BIT(12)
    109 #define VPP_MISC_POSTBLEND		__BIT(7)
    110 #define VPP_MISC_PREBLEND		__BIT(6)
    111 
    112 #define VPP_OSD_VSC_PHASE_STEP_FORMAT	__BITS(27,0)
    113 
    114 #define VPP_OSD_VSC_INI_PHASE_0		__BITS(31,16)
    115 #define VPP_OSD_VSC_INI_PHASE_1		__BITS(15,0)
    116 
    117 #define VPP_OSD_VSC_CTRL0_VSCALE_EN	__BIT(24)
    118 #define VPP_OSC_VSC_CTRL0_INTERLACE	__BIT(23)
    119 #define VPP_OSD_VSC_CTRL0_BOT_RPT_P0_NUM0	__BITS(17,16)
    120 #define VPP_OSD_VSC_CTRL0_BOT_INI_RCV_NUM0	__BITS(14,11)
    121 #define VPP_OSD_VSC_CTRL0_TOP_RPT_P0_NUM0	__BITS(9,8)
    122 #define VPP_OSD_VSC_CTRL0_TOP_INI_RCV_NUM0	__BITS(6,3)
    123 #define VPP_OSD_VSC_CTRL0_BANK_LENGTH	__BITS(2,0)
    124 
    125 #define VPP_OSD_HSC_PHASE_STEP_FORMAT	__BITS(27,0)
    126 
    127 #define VPP_OSD_HSC_INI_PHASE_0		__BITS(31,16)
    128 #define VPP_OSD_HSC_INI_PHASE_1		__BITS(15,0)
    129 
    130 #define VPP_OSD_HSC_CTRL0_HSCALE_EN	__BIT(22)
    131 #define VPP_OSD_HSC_CTRL0_RPT_P0_NUM0	__BITS(9,8)
    132 #define VPP_OSD_HSC_CTRL0_INI_RCV_NUM0	__BITS(6,3)
    133 #define VPP_OSD_HSC_CTRL0_BANK_LENGTH	__BITS(2,0)
    134 
    135 #define VPP_OSD_SC_CTRL0_OSC_SC_DIN_OSD1_ALPHA_MODE	__BIT(14)
    136 #define VPP_OSD_SC_CTRL0_OSC_SC_DIN_OSD2_ALPHA_MODE	__BIT(13)
    137 #define VPP_OSD_SC_CTRL0_OSC_SC_ALPHA_MODE		__BIT(12)
    138 #define VPP_OSD_SC_CTRL0_DEFAULT_ALPHA	__BITS(11,4)
    139 #define VPP_OSD_SC_CTRL0_OSD_SC_PATH_EN	__BIT(3)
    140 #define VPP_OSD_SC_CTRL0_OSD_SC_SEL	__BITS(1,0)
    141 
    142 #define VPP_OSD_SCI_WH_M1_WIDTH		__BITS(28,16)
    143 #define VPP_OSD_SCI_WH_M1_HEIGHT	__BITS(12,0)
    144 
    145 #define VPP_OSD_SCO_H_START		__BITS(28,16)
    146 #define VPP_OSD_SCO_H_END		__BITS(12,0)
    147 
    148 #define VPP_OSD_SCO_V_START		__BITS(28,16)
    149 #define VPP_OSD_SCO_V_END		__BITS(12,0)
    150 
    151 #endif /* _MESON_VPUREG_H */
    152