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      1 /* 	$NetBSD: xlcomreg.h,v 1.1 2006/12/02 22:18:47 freza Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2006 Jachym Holecek
      5  * All rights reserved.
      6  *
      7  * Written for DFC Design, s.r.o.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  *
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  *
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _VIRTEX_DEV_XLCOMREG_H_
     33 #define _VIRTEX_DEV_XLCOMREG_H_
     34 
     35 /*
     36  * Xilinx UART Lite (opb_uartlite_0 in EDK) registers. Note that all
     37  * line parameter are hardcoded at synthesis time. There is no hardware
     38  * flow control, just RX and TX signals.
     39  */
     40 
     41 #define XLCOM_SIZE 		0x0c
     42 
     43 /* 16B FIFOs */
     44 #define XLCOM_RX_FIFO 		0x0000
     45 #define XLCOM_TX_FIFO 		0x0004
     46 
     47 #define XLCOM_STAT 		0x0008 		/* ro */
     48 #define STAT_PARITY_ERR 	0x80
     49 #define STAT_FRAME_ERR 		0x40
     50 #define STAT_OVERRUN_ERR 	0x20
     51 #define STAT_INTR_EN 		0x10 		/* Interrupt enabled */
     52 #define STAT_TX_FULL 		0x08
     53 #define STAT_TX_EMPTY 		0x04
     54 #define STAT_RX_FULL 		0x02
     55 #define STAT_RX_DATA 	 	0x01 		/* RX FIFO has valid data */
     56 
     57 #define XLCOM_CNTL 		0x000c 		/* wo */
     58 #define CNTL_INTR_EN 		0x10
     59 #define CNTL_RX_CLEAR 		0x02 		/* Reset/clear FIFOs */
     60 #define CNTL_TX_CLEAR 		0x01
     61 
     62 #endif /*_VIRTEX_DEV_XLCOMREG_H_*/
     63