| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/sec2/ |
| priv.h | 22 const struct nvkm_acr_lsf_func *acr; member in struct:nvkm_sec2_fwif
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/ |
| secboot.h | 47 struct nvkm_acr *acr; member in struct:nvkm_secboot
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/acr/ |
| nouveau_nvkm_subdev_acr_lsfw.c | 45 nvkm_acr_lsfw_del_all(struct nvkm_acr *acr)
48 list_for_each_entry_safe(lsfw, lsft, &acr->lsfw, head) {
54 nvkm_acr_lsfw_get(struct nvkm_acr *acr, enum nvkm_acr_lsf_id id)
57 list_for_each_entry(lsfw, &acr->lsfw, head) {
65 nvkm_acr_lsfw_add(const struct nvkm_acr_lsf_func *func, struct nvkm_acr *acr,
70 if (!acr)
73 lsfw = nvkm_acr_lsfw_get(acr, id);
75 nvkm_error(&acr->subdev, "LSFW %d redefined\n", id);
84 list_add_tail(&lsfw->head, &acr->lsfw);
100 struct nvkm_acr *acr = subdev->device->acr local in function:nvkm_acr_lsfw_load_sig_image_desc_
193 struct nvkm_acr *acr = subdev->device->acr; local in function:nvkm_acr_lsfw_load_bl_inst_data_sig
[all...] |
| nouveau_nvkm_subdev_acr_base.c | 34 nvkm_acr_hsf_find(struct nvkm_acr *acr, const char *name)
37 list_for_each_entry(hsf, &acr->hsf, head) {
45 nvkm_acr_hsf_boot(struct nvkm_acr *acr, const char *name)
47 struct nvkm_subdev *subdev = &acr->subdev;
51 hsf = nvkm_acr_hsf_find(acr, name);
60 ret = hsf->func->boot(acr, hsf);
72 nvkm_acr_unload(struct nvkm_acr *acr)
74 if (acr->done) {
75 nvkm_acr_hsf_boot(acr, "unload");
76 acr->done = false
129 struct nvkm_acr *acr = device->acr; local in function:nvkm_acr_falcon
146 struct nvkm_acr *acr = device->acr; local in function:nvkm_acr_bootstrap_falcons
174 struct nvkm_acr *acr = device->acr; local in function:nvkm_acr_managed_falcon
216 struct nvkm_acr *acr = nvkm_acr(subdev); local in function:nvkm_acr_oneinit
329 struct nvkm_acr *acr = nvkm_acr(subdev); local in function:nvkm_acr_dtor
391 struct nvkm_acr *acr; local in function:nvkm_acr_new_
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/ |
| priv.h | 60 const struct nvkm_acr_lsf_func *acr; member in struct:nvkm_pmu_fwif
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_audio.c | 88 const struct radeon_hdmi_acr *acr);
90 const struct radeon_hdmi_acr *acr);
92 const struct radeon_hdmi_acr *acr);
580 pr_warn("Calculated ACR N value is too small. You may experience audio problems.\n");
582 pr_warn("Calculated ACR N value is too large. You may experience audio problems.\n");
587 DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
629 const struct radeon_hdmi_acr *acr = radeon_audio_acr(clock); local in function:radeon_audio_update_acr
637 radeon_encoder->audio->update_acr(encoder, dig->afmt->offset, acr);
|
| /src/sys/arch/sgimips/dev/ |
| scnvar.h | 102 u_char mode; /* ACR[7] + MR0[2:0] */
103 u_char acr; /* ACR[6:0]*/ member in struct:duart
|
| scn.c | 239 /* speed table groups ACR[7] */
243 /* combo of MR0[2:0] and ACR[7] */
410 u_char acr, csr, mr1, mr2; local in function:scn_setchip
475 acr = dp->acr | (dp->mode & ACR_BRG);
476 dp->base[DU_ACR] = acr; /* write-only reg! */
1002 duart->acr = 0;
1003 duart->acr |= ACR_CT_TCLK1; /* timer mode 1x clk */
1007 duart->acr |= ACR_DELTA_DCDA; /* Set CD int */
1009 duart->acr |= ACR_DELTA_DCDB; /* Set CD int *
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/core/ |
| device.h | 144 struct nvkm_acr *acr; member in struct:nvkm_device
221 int (*acr )(struct nvkm_device *, int idx, struct nvkm_acr **); member in struct:nvkm_device_chip
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 1492 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); local in function:dce_v10_0_afmt_update_ACR
1498 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1501 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1505 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1508 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1512 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1515 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1683 /* allow hw to sent ACR packets when required */
|
| amdgpu_dce_v11_0.c | 1534 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); local in function:dce_v11_0_afmt_update_ACR
1540 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1543 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1547 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1550 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1554 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1557 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1725 /* allow hw to sent ACR packets when required */
|
| amdgpu_dce_v6_0.c | 1417 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); local in function:dce_v6_0_audio_set_acr
1429 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1432 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1436 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1439 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1443 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1446 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
|
| amdgpu_dce_v8_0.c | 1455 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); local in function:dce_v8_0_afmt_update_ACR
1460 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1461 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1463 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1464 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1466 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1467 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1617 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1621 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
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