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      1 /*	$NetBSD: amdgpu_ctx.h,v 1.2 2021/12/18 23:44:58 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2018 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 #ifndef __AMDGPU_CTX_H__
     26 #define __AMDGPU_CTX_H__
     27 
     28 #include "amdgpu_ring.h"
     29 
     30 struct drm_device;
     31 struct drm_file;
     32 struct amdgpu_fpriv;
     33 
     34 #define AMDGPU_MAX_ENTITY_NUM 4
     35 
     36 struct amdgpu_ctx_entity {
     37 	uint64_t		sequence;
     38 	struct drm_sched_entity	entity;
     39 	struct dma_fence	*fences[];
     40 };
     41 
     42 struct amdgpu_ctx {
     43 	struct kref			refcount;
     44 	struct amdgpu_device		*adev;
     45 	unsigned			reset_counter;
     46 	unsigned			reset_counter_query;
     47 	uint32_t			vram_lost_counter;
     48 	spinlock_t			ring_lock;
     49 	struct amdgpu_ctx_entity	*entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];
     50 	bool				preamble_presented;
     51 	enum drm_sched_priority		init_priority;
     52 	enum drm_sched_priority		override_priority;
     53 	struct mutex			lock;
     54 	atomic_t			guilty;
     55 	unsigned long			ras_counter_ce;
     56 	unsigned long			ras_counter_ue;
     57 };
     58 
     59 struct amdgpu_ctx_mgr {
     60 	struct amdgpu_device	*adev;
     61 	struct mutex		lock;
     62 	/* protected by lock */
     63 	struct idr		ctx_handles;
     64 };
     65 
     66 extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
     67 
     68 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
     69 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
     70 
     71 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
     72 			  u32 ring, struct drm_sched_entity **entity);
     73 void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
     74 			  struct drm_sched_entity *entity,
     75 			  struct dma_fence *fence, uint64_t *seq);
     76 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
     77 				       struct drm_sched_entity *entity,
     78 				       uint64_t seq);
     79 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
     80 				  enum drm_sched_priority priority);
     81 
     82 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
     83 		     struct drm_file *filp);
     84 
     85 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
     86 			       struct drm_sched_entity *entity);
     87 
     88 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
     89 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
     90 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
     91 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
     92 
     93 void amdgpu_ctx_init_sched(struct amdgpu_device *adev);
     94 
     95 
     96 #endif
     97