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      1 /*	$NetBSD: amdgpu_vce.h,v 1.3 2021/12/18 23:44:58 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2014 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 
     26 #ifndef __AMDGPU_VCE_H__
     27 #define __AMDGPU_VCE_H__
     28 
     29 #define AMDGPU_MAX_VCE_HANDLES	16
     30 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
     31 
     32 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
     33 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
     34 
     35 #define AMDGPU_VCE_FW_53_45	((53 << 24) | (45 << 16))
     36 
     37 struct amdgpu_vce {
     38 	struct amdgpu_bo	*vcpu_bo;
     39 	uint64_t		gpu_addr;
     40 	void			*cpu_addr;
     41 	void			*saved_bo;
     42 	unsigned		fw_version;
     43 	unsigned		fb_version;
     44 	atomic_t		handles[AMDGPU_MAX_VCE_HANDLES];
     45 	struct drm_file		*filp[AMDGPU_MAX_VCE_HANDLES];
     46 	uint32_t		img_size[AMDGPU_MAX_VCE_HANDLES];
     47 	struct delayed_work	idle_work;
     48 	struct mutex		idle_mutex;
     49 	const struct firmware	*fw;	/* VCE firmware */
     50 	struct amdgpu_ring	ring[AMDGPU_MAX_VCE_RINGS];
     51 	struct amdgpu_irq_src	irq;
     52 	unsigned		harvest_config;
     53 	struct drm_sched_entity	entity;
     54 	uint32_t                srbm_soft_reset;
     55 	unsigned		num_rings;
     56 };
     57 
     58 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size);
     59 int amdgpu_vce_sw_fini(struct amdgpu_device *adev);
     60 int amdgpu_vce_entity_init(struct amdgpu_device *adev);
     61 int amdgpu_vce_suspend(struct amdgpu_device *adev);
     62 int amdgpu_vce_resume(struct amdgpu_device *adev);
     63 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
     64 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
     65 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx);
     66 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
     67 				struct amdgpu_ib *ib, uint32_t flags);
     68 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
     69 				unsigned flags);
     70 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
     71 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout);
     72 void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring);
     73 void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring);
     74 unsigned amdgpu_vce_ring_get_emit_ib_size(struct amdgpu_ring *ring);
     75 unsigned amdgpu_vce_ring_get_dma_frame_size(struct amdgpu_ring *ring);
     76 
     77 #endif
     78