| /xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/ |
| genX_state.c | 49 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) { function
69 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) { function
84 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { function
107 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
122 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
128 anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
130 anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
140 anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
149 anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
167 anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp)
[all...] |
| genX_pipeline.c | 183 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
225 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS), sgvs) {
251 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
291 anv_batch_emit(batch, GEN7_PIPE_CONTROL, pc) { function
299 anv_batch_emit(batch, GENX(3DSTATE_URB_VS), urb) { function
331 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE), sbe);
333 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE_SWIZ), sbe);
577 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE), ms) {
609 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK), sm) {
1041 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_BLEND), blend)
[all...] |
| genX_cmd_buffer.c | 45 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { function
68 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
74 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
190 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
516 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
531 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
641 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
684 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
796 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
803 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi)
3673 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { function
3681 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { function
3689 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { function
3696 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { function
3707 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { function
3720 anv_batch_emit(batch, GENX(GPGPU_WALKER), ggw) { function
[all...] |
| anv_private.h | 1453 #define anv_batch_emit(batch, cmd, name) \ macro
|
| /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/ |
| genX_state.c | 101 anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) { function
106 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) { function
130 anv_batch_emit(batch, GENX(3DSTATE_SUBSLICE_HASH_TABLE), p) {
148 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), p) {
166 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
185 anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
187 anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
197 anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
209 anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
280 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri)
481 anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) { function
541 anv_batch_emit(batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) { function
606 anv_batch_emit(batch, GENX(3DSTATE_CPS), cps) { function
629 anv_batch_emit(batch, GENX(3DSTATE_CPS_POINTERS), cps) { function
[all...] |
| genX_pipeline.c | 185 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
226 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
233 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_SGVS), sgvs) {
259 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
294 anv_batch_emit(batch, GFX7_PIPE_CONTROL, pc) { function
302 anv_batch_emit(batch, GENX(3DSTATE_URB_VS), urb) { function
336 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_SBE), sbe);
338 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_SBE_SWIZ), sbe);
847 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_SAMPLE_MASK), sm) {
1389 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS_BLEND), _blend
[all...] |
| genX_cmd_buffer.c | 107 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
139 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
272 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
783 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
798 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
889 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
932 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
1046 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
1053 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
1897 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc)
5067 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { function
5075 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { function
5083 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { function
5090 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { function
5101 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { function
7030 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) { function
[all...] |
| anv_private.h | 1734 #define anv_batch_emit(batch, cmd, name) \ macro
1749 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { \
|
