Home | History | Annotate | Line # | Download | only in ic
      1 /*	$NetBSD: athvar.h,v 1.36 2013/01/27 12:48:56 jmcneill Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer,
     12  *    without modification.
     13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
     14  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
     15  *    redistribution must be conditioned upon including a substantially
     16  *    similar Disclaimer requirement for further binary redistribution.
     17  * 3. Neither the names of the above-listed copyright holders nor the names
     18  *    of any contributors may be used to endorse or promote products derived
     19  *    from this software without specific prior written permission.
     20  *
     21  * Alternatively, this software may be distributed under the terms of the
     22  * GNU General Public License ("GPL") version 2 as published by the Free
     23  * Software Foundation.
     24  *
     25  * NO WARRANTY
     26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     28  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
     29  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
     30  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
     31  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
     34  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
     36  * THE POSSIBILITY OF SUCH DAMAGES.
     37  *
     38  * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.29 2005/08/08 18:46:36 sam Exp $
     39  */
     40 
     41 /*
     42  * Defintions for the Atheros Wireless LAN controller driver.
     43  */
     44 #ifndef _DEV_ATH_ATHVAR_H
     45 #define _DEV_ATH_ATHVAR_H
     46 
     47 #include <net/if.h>
     48 #include <net/if_media.h>
     49 #include <net/if_ether.h>
     50 
     51 #include <net80211/ieee80211_netbsd.h>
     52 #include <net80211/ieee80211_var.h>
     53 #include <net80211/ieee80211_radiotap.h>
     54 
     55 #include <external/isc/atheros_hal/dist/ah.h>
     56 
     57 #include <dev/ic/ath_netbsd.h>
     58 #include <dev/ic/athioctl.h>
     59 #include <dev/ic/athrate.h>
     60 
     61 #define	ATH_TIMEOUT		1000
     62 
     63 #ifndef ATH_RXBUF
     64 #define	ATH_RXBUF	40		/* number of RX buffers */
     65 #endif
     66 #ifndef ATH_TXBUF
     67 #define	ATH_TXBUF	200		/* number of TX buffers */
     68 #endif
     69 #define	ATH_TXDESC	10		/* number of descriptors per buffer */
     70 #define	ATH_TXMAXTRY	11		/* max number of transmit attempts */
     71 #define	ATH_TXMGTTRY	4		/* xmit attempts for mgt/ctl frames */
     72 #define	ATH_TXINTR_PERIOD 5		/* max number of batched tx descriptors */
     73 
     74 #define	ATH_BEACON_AIFS_DEFAULT	 0	/* default aifs for ap beacon q */
     75 #define	ATH_BEACON_CWMIN_DEFAULT 0	/* default cwmin for ap beacon q */
     76 #define	ATH_BEACON_CWMAX_DEFAULT 0	/* default cwmax for ap beacon q */
     77 
     78 /*
     79  * The key cache is used for h/w cipher state and also for
     80  * tracking station state such as the current tx antenna.
     81  * We also setup a mapping table between key cache slot indices
     82  * and station state to short-circuit node lookups on rx.
     83  * Different parts have different size key caches.  We handle
     84  * up to ATH_KEYMAX entries (could dynamically allocate state).
     85  */
     86 #define	ATH_KEYMAX	128		/* max key cache size we handle */
     87 #define	ATH_KEYBYTES	(ATH_KEYMAX/NBBY)	/* storage space in bytes */
     88 /*
     89  * Convert from net80211 layer values to Ath layer values. Hopefully this will
     90  * be optimised away when the two constants are the same.
     91  */
     92 typedef unsigned int ath_keyix_t;
     93 #define ATH_KEY(_keyix) ((_keyix == IEEE80211_KEYIX_NONE) ? HAL_TXKEYIX_INVALID : _keyix)
     94 
     95 /* driver-specific node state */
     96 struct ath_node {
     97 	struct ieee80211_node an_node;	/* base class */
     98 	u_int32_t	an_avgrssi;	/* average rssi over all rx frames */
     99 	/* variable-length rate control state follows */
    100 };
    101 #define	ATH_NODE(ni)	((struct ath_node *)(ni))
    102 #define	ATH_NODE_CONST(ni)	((const struct ath_node *)(ni))
    103 
    104 #define ATH_RSSI_LPF_LEN	10
    105 #define ATH_RSSI_DUMMY_MARKER	0x127
    106 #define ATH_EP_MUL(x, mul)	((x) * (mul))
    107 #define ATH_RSSI_IN(x)		(ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
    108 #define ATH_LPF_RSSI(x, y, len) \
    109     ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
    110 #define ATH_RSSI_LPF(x, y) do {						\
    111     if ((y) >= -20)							\
    112     	x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN);	\
    113 } while (0)
    114 
    115 struct ath_buf {
    116 	STAILQ_ENTRY(ath_buf)	bf_list;
    117 #define bf_nseg		bf_dmamap->dm_nsegs
    118 	int			bf_flags;	/* tx descriptor flags */
    119 	struct ath_desc		*bf_desc;	/* virtual addr of desc */
    120 	bus_addr_t		bf_daddr;	/* physical addr of desc */
    121 	bus_dmamap_t		bf_dmamap;	/* DMA map for mbuf chain */
    122 	struct mbuf		*bf_m;		/* mbuf for buf */
    123 	struct ieee80211_node	*bf_node;	/* pointer to the node */
    124 #define bf_mapsize	bf_dmamap->dm_mapsize
    125 #define	ATH_MAX_SCATTER		ATH_TXDESC	/* max(tx,rx,beacon) desc's */
    126 #define bf_segs		bf_dmamap->dm_segs
    127 };
    128 typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
    129 
    130 /*
    131  * DMA state for tx/rx descriptors.
    132  */
    133 struct ath_descdma {
    134 	const char*		dd_name;
    135 	struct ath_desc		*dd_desc;	/* descriptors */
    136 	bus_addr_t		dd_desc_paddr;	/* physical addr of dd_desc */
    137 	bus_size_t		dd_desc_len;	/* size of dd_desc */
    138 	bus_dma_segment_t	dd_dseg;
    139 	int			dd_dnseg;	/* number of segments */
    140 	bus_dma_tag_t		dd_dmat;	/* bus DMA tag */
    141 	bus_dmamap_t		dd_dmamap;	/* DMA map for descriptors */
    142 	struct ath_buf		*dd_bufptr;	/* associated buffers */
    143 };
    144 
    145 /*
    146  * Data transmit queue state.  One of these exists for each
    147  * hardware transmit queue.  Packets sent to us from above
    148  * are assigned to queues based on their priority.  Not all
    149  * devices support a complete set of hardware transmit queues.
    150  * For those devices the array sc_ac2q will map multiple
    151  * priorities to fewer hardware queues (typically all to one
    152  * hardware queue).
    153  */
    154 struct ath_txq {
    155 	u_int			axq_qnum;	/* hardware q number */
    156 	u_int			axq_depth;	/* queue depth (stat only) */
    157 	u_int			axq_intrcnt;	/* interrupt count */
    158 	u_int32_t		*axq_link;	/* link ptr in last TX desc */
    159 	STAILQ_HEAD(, ath_buf)	axq_q;		/* transmit queue */
    160 	ath_txq_lock_t		axq_lock;	/* lock on q and link */
    161 	/*
    162 	 * State for patching up CTS when bursting.
    163 	 */
    164 	struct	ath_buf		*axq_linkbuf;	/* va of last buffer */
    165 	u_int			axq_timer;	/* transmit timeout */
    166 };
    167 
    168 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
    169 	STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
    170 	(_tq)->axq_depth++; \
    171 	(_tq)->axq_timer = 5; \
    172 } while (0)
    173 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
    174 	STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
    175 	if (--(_tq)->axq_depth == 0) \
    176 		(_tq)->axq_timer = 0; \
    177 } while (0)
    178 
    179 struct taskqueue;
    180 struct ath_tx99;
    181 
    182 struct ath_softc {
    183 	device_t 		sc_dev;
    184 	device_suspensor_t	sc_suspensor;
    185 	pmf_qual_t		sc_qual;
    186 	struct ethercom		sc_ec;		/* interface common */
    187 	struct ath_stats	sc_stats;	/* interface statistics */
    188 	struct ieee80211com	sc_ic;		/* IEEE 802.11 common */
    189 	void			(*sc_power)(struct ath_softc *, int);
    190 	int			sc_regdomain;
    191 	int			sc_countrycode;
    192 	int			sc_debug;
    193 	struct sysctllog	*sc_sysctllog;
    194 	void			(*sc_recv_mgmt)(struct ieee80211com *,
    195 					struct mbuf *,
    196 					struct ieee80211_node *,
    197 					int, int, u_int32_t);
    198 	int			(*sc_newstate)(struct ieee80211com *,
    199 					enum ieee80211_state, int);
    200 	void 			(*sc_node_free)(struct ieee80211_node *);
    201 	HAL_BUS_TAG		sc_st;		/* bus space tag */
    202 	HAL_BUS_HANDLE		sc_sh;		/* bus space handle */
    203 	bus_dma_tag_t		sc_dmat;	/* bus DMA tag */
    204 	struct ath_hal		*sc_ah;		/* Atheros HAL */
    205 	struct ath_ratectrl	*sc_rc;		/* tx rate control support */
    206 	struct ath_tx99		*sc_tx99;	/* tx99 adjunct state */
    207 	void			(*sc_setdefantenna)(struct ath_softc *, u_int);
    208 	unsigned int		sc_mrretry : 1,	/* multi-rate retry support */
    209 				sc_softled : 1,	/* enable LED gpio status */
    210 				sc_splitmic: 1,	/* split TKIP MIC keys */
    211 				sc_needmib : 1,	/* enable MIB stats intr */
    212 				sc_diversity : 1,/* enable rx diversity */
    213 				sc_hasveol : 1,	/* tx VEOL support */
    214 				sc_ledstate: 1,	/* LED on/off state */
    215 				sc_blinking: 1,	/* LED blink operation active */
    216 				sc_mcastkey: 1,	/* mcast key cache search */
    217 				sc_syncbeacon:1,/* sync/resync beacon timers */
    218 				sc_hasclrkey:1;	/* CLR key supported */
    219 						/* rate tables */
    220 	const HAL_RATE_TABLE	*sc_rates[IEEE80211_MODE_MAX];
    221 	const HAL_RATE_TABLE	*sc_currates;	/* current rate table */
    222 	enum ieee80211_phymode	sc_curmode;	/* current phy mode */
    223 	u_int16_t		sc_curtxpow;	/* current tx power limit */
    224 	HAL_CHANNEL		sc_curchan;	/* current h/w channel */
    225 	u_int8_t		sc_rixmap[256];	/* IEEE to h/w rate table ix */
    226 	struct {
    227 		u_int8_t	ieeerate;	/* IEEE rate */
    228 		u_int8_t	rxflags;	/* radiotap rx flags */
    229 		u_int8_t	txflags;	/* radiotap tx flags */
    230 		u_int16_t	ledon;		/* softled on time */
    231 		u_int16_t	ledoff;		/* softled off time */
    232 	} sc_hwmap[32];				/* h/w rate ix mappings */
    233 	u_int8_t		sc_minrateix;	/* min h/w rate index */
    234 	u_int8_t		sc_mcastrix;	/* mcast h/w rate index */
    235 	u_int8_t		sc_protrix;	/* protection rate index */
    236 	u_int			sc_mcastrate;	/* ieee rate for mcastrateix */
    237 	u_int			sc_txantenna;	/* tx antenna (fixed or auto) */
    238 	HAL_INT			sc_imask;	/* interrupt mask copy */
    239 	u_int			sc_keymax;	/* size of key cache */
    240 	u_int8_t		sc_keymap[ATH_KEYBYTES];/* key use bit map */
    241 
    242 	u_int			sc_ledpin;	/* GPIO pin for driving LED */
    243 	u_int			sc_ledon;	/* pin setting for LED on */
    244 	u_int			sc_ledidle;	/* idle polling interval */
    245 	int			sc_ledevent;	/* time of last LED event */
    246 	u_int8_t		sc_rxrate;	/* current rx rate for LED */
    247 	u_int8_t		sc_txrate;	/* current tx rate for LED */
    248 	u_int16_t		sc_ledoff;	/* off time for current blink */
    249 	struct callout		sc_ledtimer;	/* led off timer */
    250 
    251 	struct bpf_if *		sc_drvbpf;
    252 	union {
    253 		struct ath_tx_radiotap_header th;
    254 		u_int8_t	pad[64];
    255 	} u_tx_rt;
    256 	int			sc_tx_th_len;
    257 	union {
    258 		struct ath_rx_radiotap_header th;
    259 		u_int8_t	pad[64];
    260 	} u_rx_rt;
    261 	int			sc_rx_th_len;
    262 
    263 	ath_task_t		sc_fataltask;	/* fatal int processing */
    264 
    265 	struct ath_descdma	sc_rxdma;	/* RX descriptos */
    266 	ath_bufhead		sc_rxbuf;	/* receive buffer */
    267 	u_int32_t		*sc_rxlink;	/* link ptr in last RX desc */
    268 	ath_task_t		sc_rxtask;	/* rx int processing */
    269 	ath_task_t		sc_rxorntask;	/* rxorn int processing */
    270 	ath_task_t		sc_radartask;	/* radar processing */
    271 	u_int8_t		sc_defant;	/* current default antenna */
    272 	u_int8_t		sc_rxotherant;	/* rx's on non-default antenna*/
    273 	u_int64_t		sc_lastrx;	/* tsf of last rx'd frame */
    274 
    275 	struct ath_descdma	sc_txdma;	/* TX descriptors */
    276 	ath_bufhead		sc_txbuf;	/* transmit buffer */
    277 	ath_txbuf_lock_t	sc_txbuflock;	/* txbuf lock */
    278 	u_int			sc_txqsetup;	/* h/w queues setup */
    279 	u_int			sc_txintrperiod;/* tx interrupt batching */
    280 	struct ath_txq		sc_txq[HAL_NUM_TX_QUEUES];
    281 	struct ath_txq		*sc_ac2q[5];	/* WME AC -> h/w q map */
    282 	ath_task_t		sc_txtask;	/* tx int processing */
    283 
    284 	struct ath_descdma	sc_bdma;	/* beacon descriptors */
    285 	ath_bufhead		sc_bbuf;	/* beacon buffers */
    286 	u_int			sc_bhalq;	/* HAL q for outgoing beacons */
    287 	u_int			sc_bmisscount;	/* missed beacon transmits */
    288 	u_int32_t		sc_ant_tx[8];	/* recent tx frames/antenna */
    289 	struct ath_txq		*sc_cabq;	/* tx q for cab frames */
    290 	struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */
    291 	ath_task_t		sc_bmisstask;	/* bmiss int processing */
    292 	ath_task_t		sc_bstucktask;	/* stuck beacon processing */
    293 	enum {
    294 		OK,				/* no change needed */
    295 		UPDATE,				/* update pending */
    296 		COMMIT				/* beacon sent, commit change */
    297 	} sc_updateslot;			/* slot time update fsm */
    298 
    299 	struct callout		sc_cal_ch;	/* callout handle for cals */
    300 	int			sc_calinterval;	/* current polling interval */
    301 	int			sc_caltries;	/* cals at current interval */
    302 	HAL_NODE_STATS		sc_halstats;	/* station-mode rssi stats */
    303 	struct callout		sc_scan_ch;	/* callout handle for scan */
    304 	struct callout		sc_dfs_ch;	/* callout handle for dfs */
    305 	u_int			sc_flags;	/* misc flags */
    306 };
    307 #define	sc_if			sc_ec.ec_if
    308 #define	sc_tx_th		u_tx_rt.th
    309 #define	sc_rx_th		u_rx_rt.th
    310 
    311 #define	ATH_ATTACHED		0x0001		/* attach has succeeded */
    312 #define	ATH_KEY_UPDATING	0x0002		/* key change in progress */
    313 
    314 #define	ATH_TXQ_SETUP(sc, i)	((sc)->sc_txqsetup & (1<<i))
    315 
    316 int	ath_attach(u_int16_t, struct ath_softc *);
    317 int	ath_detach(struct ath_softc *);
    318 int	ath_activate(device_t, enum devact);
    319 bool	ath_resume(struct ath_softc *);
    320 void	ath_suspend(struct ath_softc *);
    321 int	ath_intr(void *);
    322 int	ath_reset(struct ifnet *);
    323 void	ath_sysctlattach(struct ath_softc *);
    324 
    325 extern int ath_dwelltime;
    326 extern int ath_calinterval;
    327 extern int ath_outdoor;
    328 extern int ath_xchanmode;
    329 extern int ath_countrycode;
    330 extern int ath_regdomain;
    331 extern int ath_debug;
    332 extern int ath_rxbuf;
    333 extern int ath_txbuf;
    334 
    335 /*
    336  * HAL definitions to comply with local coding convention.
    337  */
    338 #define	ath_hal_detach(_ah) \
    339 	((*(_ah)->ah_detach)((_ah)))
    340 #define	ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
    341 	((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
    342 #define	ath_hal_getratetable(_ah, _mode) \
    343 	((*(_ah)->ah_getRateTable)((_ah), (_mode)))
    344 #define	ath_hal_getmac(_ah, _mac) \
    345 	((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
    346 #define	ath_hal_setmac(_ah, _mac) \
    347 	((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
    348 #define	ath_hal_intrset(_ah, _mask) \
    349 	((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
    350 #define	ath_hal_intrget(_ah) \
    351 	((*(_ah)->ah_getInterrupts)((_ah)))
    352 #define	ath_hal_intrpend(_ah) \
    353 	((*(_ah)->ah_isInterruptPending)((_ah)))
    354 #define	ath_hal_getisr(_ah, _pmask) \
    355 	((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
    356 #define	ath_hal_updatetxtriglevel(_ah, _inc) \
    357 	((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
    358 #define	ath_hal_setpower(_ah, _mode) \
    359 	((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
    360 #define	ath_hal_keycachesize(_ah) \
    361 	((*(_ah)->ah_getKeyCacheSize)((_ah)))
    362 #define	ath_hal_keyreset(_ah, _ix) \
    363 	((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
    364 #define	ath_hal_keyset(_ah, _ix, _pk, _mac) \
    365 	((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
    366 #define	ath_hal_keyisvalid(_ah, _ix) \
    367 	(((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
    368 #define	ath_hal_keysetmac(_ah, _ix, _mac) \
    369 	((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
    370 #define	ath_hal_getrxfilter(_ah) \
    371 	((*(_ah)->ah_getRxFilter)((_ah)))
    372 #define	ath_hal_setrxfilter(_ah, _filter) \
    373 	((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
    374 #define	ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
    375 	((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
    376 #define	ath_hal_waitforbeacon(_ah, _bf) \
    377 	((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
    378 #define	ath_hal_putrxbuf(_ah, _bufaddr) \
    379 	((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
    380 #define	ath_hal_gettsf32(_ah) \
    381 	((*(_ah)->ah_getTsf32)((_ah)))
    382 #define	ath_hal_gettsf64(_ah) \
    383 	((*(_ah)->ah_getTsf64)((_ah)))
    384 #define	ath_hal_resettsf(_ah) \
    385 	((*(_ah)->ah_resetTsf)((_ah)))
    386 #define	ath_hal_rxena(_ah) \
    387 	((*(_ah)->ah_enableReceive)((_ah)))
    388 #define	ath_hal_puttxbuf(_ah, _q, _bufaddr) \
    389 	((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
    390 #define	ath_hal_gettxbuf(_ah, _q) \
    391 	((*(_ah)->ah_getTxDP)((_ah), (_q)))
    392 #define	ath_hal_numtxpending(_ah, _q) \
    393 	((*(_ah)->ah_numTxPending)((_ah), (_q)))
    394 #define	ath_hal_getrxbuf(_ah) \
    395 	((*(_ah)->ah_getRxDP)((_ah)))
    396 #define	ath_hal_txstart(_ah, _q) \
    397 	((*(_ah)->ah_startTxDma)((_ah), (_q)))
    398 #define	ath_hal_setchannel(_ah, _chan) \
    399 	((*(_ah)->ah_setChannel)((_ah), (_chan)))
    400 #define	ath_hal_calibrate(_ah, _chan, _iqcal) \
    401 	((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
    402 #define	ath_hal_setledstate(_ah, _state) \
    403 	((*(_ah)->ah_setLedState)((_ah), (_state)))
    404 #define	ath_hal_beaconinit(_ah, _nextb, _bperiod) \
    405 	((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
    406 #define	ath_hal_beaconreset(_ah) \
    407 	((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
    408 #define	ath_hal_beacontimers(_ah, _bs) \
    409 	((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
    410 #define	ath_hal_setassocid(_ah, _bss, _associd) \
    411 	((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
    412 #define	ath_hal_phydisable(_ah) \
    413 	((*(_ah)->ah_phyDisable)((_ah)))
    414 #define	ath_hal_setopmode(_ah) \
    415 	((*(_ah)->ah_setPCUConfig)((_ah)))
    416 #define	ath_hal_stoptxdma(_ah, _qnum) \
    417 	((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
    418 #define	ath_hal_stoppcurecv(_ah) \
    419 	((*(_ah)->ah_stopPcuReceive)((_ah)))
    420 #define	ath_hal_startpcurecv(_ah) \
    421 	((*(_ah)->ah_startPcuReceive)((_ah)))
    422 #define	ath_hal_stopdmarecv(_ah) \
    423 	((*(_ah)->ah_stopDmaReceive)((_ah)))
    424 #define	ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
    425 	((*(_ah)->ah_getDiagState)((_ah), (_id), \
    426 		(_indata), (_insize), (_outdata), (_outsize)))
    427 #define	ath_hal_setuptxqueue(_ah, _type, _irq) \
    428 	((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
    429 #define	ath_hal_resettxqueue(_ah, _q) \
    430 	((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
    431 #define	ath_hal_releasetxqueue(_ah, _q) \
    432 	((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
    433 #define	ath_hal_gettxqueueprops(_ah, _q, _qi) \
    434 	((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
    435 #define	ath_hal_settxqueueprops(_ah, _q, _qi) \
    436 	((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
    437 #define	ath_hal_getrfgain(_ah) \
    438 	((*(_ah)->ah_getRfGain)((_ah)))
    439 #define	ath_hal_getdefantenna(_ah) \
    440 	((*(_ah)->ah_getDefAntenna)((_ah)))
    441 #define	ath_hal_setdefantenna(_ah, _ant) \
    442 	((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
    443 #define	ath_hal_rxmonitor(_ah, _arg, _chan) \
    444 	((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
    445 #define	ath_hal_mibevent(_ah, _stats) \
    446 	((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
    447 #define	ath_hal_setslottime(_ah, _us) \
    448 	((*(_ah)->ah_setSlotTime)((_ah), (_us)))
    449 #define	ath_hal_getslottime(_ah) \
    450 	((*(_ah)->ah_getSlotTime)((_ah)))
    451 #define	ath_hal_setacktimeout(_ah, _us) \
    452 	((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
    453 #define	ath_hal_getacktimeout(_ah) \
    454 	((*(_ah)->ah_getAckTimeout)((_ah)))
    455 #define	ath_hal_setctstimeout(_ah, _us) \
    456 	((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
    457 #define	ath_hal_getctstimeout(_ah) \
    458 	((*(_ah)->ah_getCTSTimeout)((_ah)))
    459 #define	ath_hal_getcapability(_ah, _cap, _param, _result) \
    460 	((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
    461 #define	ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
    462 	((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
    463 #define	ath_hal_ciphersupported(_ah, _cipher) \
    464 	(ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
    465 #define	ath_hal_getregdomain(_ah, _prd) \
    466 	(ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
    467 #define	ath_hal_setregdomain(_ah, _rd) \
    468 	ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL)
    469 #define	ath_hal_getcountrycode(_ah, _pcc) \
    470 	(*(_pcc) = (_ah)->ah_countryCode)
    471 #define	ath_hal_gettkipmic(_ah) \
    472 	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
    473 #define	ath_hal_settkipmic(_ah, _v) \
    474 	ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
    475 #define	ath_hal_hastkipsplit(_ah) \
    476 	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
    477 #define	ath_hal_gettkipsplit(_ah) \
    478 	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
    479 #define	ath_hal_settkipsplit(_ah, _v) \
    480 	ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
    481 #define	ath_hal_haswmetkipmic(_ah) \
    482 	(ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
    483 #define	ath_hal_hwphycounters(_ah) \
    484 	(ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
    485 #define	ath_hal_hasdiversity(_ah) \
    486 	(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
    487 #define	ath_hal_getdiversity(_ah) \
    488 	(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
    489 #define	ath_hal_setdiversity(_ah, _v) \
    490 	ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
    491 #define	ath_hal_getdiag(_ah, _pv) \
    492 	(ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
    493 #define	ath_hal_setdiag(_ah, _v) \
    494 	ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
    495 #define	ath_hal_getnumtxqueues(_ah, _pv) \
    496 	(ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
    497 #define	ath_hal_hasveol(_ah) \
    498 	(ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
    499 #define	ath_hal_hastxpowlimit(_ah) \
    500 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
    501 #define	ath_hal_settxpowlimit(_ah, _pow) \
    502 	((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
    503 #define	ath_hal_gettxpowlimit(_ah, _ppow) \
    504 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
    505 #define	ath_hal_getmaxtxpow(_ah, _ppow) \
    506 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
    507 #define	ath_hal_gettpscale(_ah, _scale) \
    508 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
    509 #define	ath_hal_settpscale(_ah, _v) \
    510 	ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
    511 #define	ath_hal_hastpc(_ah) \
    512 	(ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
    513 #define	ath_hal_gettpc(_ah) \
    514 	(ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
    515 #define	ath_hal_settpc(_ah, _v) \
    516 	ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
    517 #define	ath_hal_hasbursting(_ah) \
    518 	(ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
    519 #ifdef notyet
    520 #define	ath_hal_hasmcastkeysearch(_ah) \
    521 	(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
    522 #define	ath_hal_getmcastkeysearch(_ah) \
    523 	(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
    524 #else
    525 #define	ath_hal_getmcastkeysearch(_ah)	0
    526 #endif
    527 #define	ath_hal_hasrfsilent(_ah) \
    528 	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
    529 #define	ath_hal_getrfkill(_ah) \
    530 	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
    531 #define	ath_hal_setrfkill(_ah, _onoff) \
    532 	ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
    533 #define	ath_hal_getrfsilent(_ah, _prfsilent) \
    534 	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
    535 #define	ath_hal_setrfsilent(_ah, _rfsilent) \
    536 	ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
    537 #define	ath_hal_gettpack(_ah, _ptpack) \
    538 	(ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
    539 #define	ath_hal_settpack(_ah, _tpack) \
    540 	ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
    541 #define	ath_hal_gettpcts(_ah, _ptpcts) \
    542 	(ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
    543 #define	ath_hal_settpcts(_ah, _tpcts) \
    544 	ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
    545 #define	ath_hal_getchannoise(_ah, _c) \
    546 	((*(_ah)->ah_getChanNoise)((_ah), (_c)))
    547 
    548 #define	ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
    549 	((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
    550 #if 0
    551 #define	ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, tsf, a5) \
    552 	((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), (tsf), (a5)))
    553 #else
    554 #define	ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
    555 	((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
    556 #endif
    557 #define	ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
    558 		_txr0, _txtr0, _keyix, _ant, _flags, \
    559 		_rtsrate, _rtsdura) \
    560 	((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
    561 		(_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
    562 		(_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
    563 #define	ath_hal_setupxtxdesc(_ah, _ds, \
    564 		_txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
    565 	((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
    566 		(_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
    567 #define	ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
    568 	((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
    569 #define	ath_hal_txprocdesc(_ah, _ds, _ts) \
    570 	((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
    571 #define	ath_hal_gettxintrtxqs(_ah, _txqs) \
    572 	((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
    573 
    574 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
    575         ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
    576 #define ath_hal_gpioset(_ah, _gpio, _b) \
    577         ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
    578 
    579 #define ath_hal_radar_event(_ah) \
    580 	((*(_ah)->ah_radarHaveEvent)((_ah)))
    581 #define ath_hal_procdfs(_ah, _chan) \
    582 	((*(_ah)->ah_processDfs)((_ah), (_chan)))
    583 #define ath_hal_checknol(_ah, _chan, _nchans) \
    584 	((*(_ah)->ah_dfsNolCheck)((_ah), (_chan), (_nchans)))
    585 
    586 #endif /* _DEV_ATH_ATHVAR_H */
    587