| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_object.c | 697 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; local in function:radeon_bo_set_tiling_flags
700 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
714 switch (bankh) {
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| radeon_atombios_crtc.c | 1161 unsigned bankw, bankh, mtaspect, tile_split; local in function:dce4_crtc_do_set_base
1283 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1350 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
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| radeon_evergreen_cs.c | 187 unsigned bankh; member in struct:eg_surface
279 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
367 switch (surf->bankh) {
368 case 0: surf->bankh = 1; break;
369 case 1: surf->bankh = 2; break;
370 case 2: surf->bankh = 4; break;
371 case 3: surf->bankh = 8; break;
373 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n",
374 __func__, __LINE__, prefix, surf->bankh);
421 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id])
1212 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_cs_handle_reg
1476 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_cs_handle_reg
1504 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_cs_handle_reg
2393 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_packet3_check
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 1994 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v10_0_crtc_do_set_base
1997 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2008 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
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| amdgpu_dce_v11_0.c | 2036 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v11_0_crtc_do_set_base
2039 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2050 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
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| amdgpu_dce_v6_0.c | 1943 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v6_0_crtc_do_set_base
1946 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1955 fb_format |= GRPH_BANK_HEIGHT(bankh);
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| amdgpu_dce_v8_0.c | 1915 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v8_0_crtc_do_set_base
1918 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1927 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm.c | 3263 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; local in function:fill_plane_buffer_attributes
3266 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
3277 tiling_info->gfx8.bank_height = bankh;
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