| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_object.c | 697 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; local in function:radeon_bo_set_tiling_flags
699 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
704 switch (bankw) {
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| radeon_atombios_crtc.c | 1161 unsigned bankw, bankh, mtaspect, tile_split; local in function:dce4_crtc_do_set_base
1283 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1349 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
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| radeon_evergreen_cs.c | 186 unsigned bankw; member in struct:eg_surface
278 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
357 switch (surf->bankw) {
358 case 0: surf->bankw = 1; break;
359 case 1: surf->bankw = 2; break;
360 case 2: surf->bankw = 4; break;
361 case 3: surf->bankw = 8; break;
363 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n",
364 __func__, __LINE__, prefix, surf->bankw);
420 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id])
1212 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_cs_handle_reg
1476 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_cs_handle_reg
1504 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_cs_handle_reg
2393 unsigned bankw, bankh, mtaspect, tile_split; local in function:evergreen_packet3_check
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 1994 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v10_0_crtc_do_set_base
1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2007 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
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| amdgpu_dce_v11_0.c | 2036 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v11_0_crtc_do_set_base
2038 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2049 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
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| amdgpu_dce_v6_0.c | 1943 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v6_0_crtc_do_set_base
1945 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1954 fb_format |= GRPH_BANK_WIDTH(bankw);
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| amdgpu_dce_v8_0.c | 1915 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v8_0_crtc_do_set_base
1917 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1926 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm.c | 3263 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; local in function:fill_plane_buffer_attributes
3265 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
3276 tiling_info->gfx8.bank_width = bankw;
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