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    Searched defs:cb_dcc_base (Results 1 - 4 of 4) sorted by relevancy

  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
si_state.c 3039 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base; local
3075 cb_dcc_base = 0;
3097 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3099 cb_dcc_base |= tex->surface.tile_swizzle;
3136 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3137 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3157 if (cb_dcc_base)
3158 cb_dcc_base += level_info->dcc_offset >> 8;
3199 radeon_emit(cs, cb_dcc_base);
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
si_state.c 3051 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base; local
3079 cb_dcc_base = 0;
3114 cb_dcc_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
3118 cb_dcc_base |= dcc_tile_swizzle;
3152 radeon_emit(cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3159 radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32);
3197 radeon_emit(cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3198 radeon_emit(S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3218 if (cb_dcc_base)
3219 cb_dcc_base += tex->surface.u.legacy.color.dcc_level[cb->base.u.tex.level].dcc_offset >> 8
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
radv_private.h 1247 uint64_t cb_dcc_base; member in struct:radv_color_buffer_info
  /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
radv_private.h 1804 uint64_t cb_dcc_base; member in struct:radv_color_buffer_info

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