| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_cdclk.h | 22 u32 cdclk; member in struct:intel_cdclk_vals
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| intel_cdclk.c | 35 * DOC: CDCLK / RAWCLK
40 * are the core display clock (CDCLK) and RAWCLK.
42 * CDCLK clocks most of the display pipe logic, and thus its frequency
47 * On several platforms the CDCLK frequency can be changed dynamically
49 * Typically changes to the CDCLK frequency require all the display pipes
52 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
53 * DMC will not change the active CDCLK frequency however, so that part
65 cdclk_state->cdclk = 133333;
71 cdclk_state->cdclk = 200000;
77 cdclk_state->cdclk = 266667
535 int cdclk = cdclk_state->cdclk; local
622 int cdclk = cdclk_state->cdclk; local
723 int cdclk = cdclk_state->cdclk; local
1000 int cdclk = cdclk_state->cdclk; local
1499 int cdclk = cdclk_state->cdclk; local
1614 int cdclk, vco; local
2122 int min_cdclk, cdclk; local
2149 int min_cdclk, cdclk; local
2216 int min_cdclk, cdclk, vco; local
2252 int min_cdclk, min_voltage_level, cdclk, vco; local
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| intel_display_types.h | 466 * Logical state of cdclk (used for all scaling, watermark,
473 * Actual state of cdclk, can be different from the logical
482 } cdclk; member in struct:intel_atomic_state
497 /* minimum acceptable cdclk for each pipe */
516 * cdclk.*
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| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_drv.h | 288 u8 (*calc_voltage_level)(int cdclk);
895 unsigned int cdclk, vco, ref, bypass; member in struct:intel_cdclk_state
1036 * The current logical cdclk state.
1037 * See intel_atomic_state.cdclk.logical
1041 * The current actual cdclk state.
1042 * See intel_atomic_state.cdclk.actual
1045 /* The current hardware cdclk state */
1048 /* cdclk, divider, and ratio table from bspec */
1052 } cdclk; member in struct:drm_i915_private
1098 /* dpll and cdclk state is protected by connection_mutex *
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