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      1 /*	$NetBSD: dmacvar.h,v 1.12 2017/08/11 07:30:01 isaki Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Minoura Makoto.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k.
     34  */
     35 
     36 #include <dev/ic/mc68450reg.h>
     37 #include <machine/bus.h>
     38 
     39 #define DMAC_MAPSIZE 64
     40 
     41 typedef int (*dmac_intr_handler_t)(void *);
     42 
     43 /*
     44  * Structure that describes a single transfer.
     45  */
     46 struct dmac_channel_stat;
     47 struct dmac_dma_xfer {
     48 	struct dmac_channel_stat *dx_channel;
     49 	bus_dmamap_t	dx_dmamap;	/* dmamap tag */
     50 	bus_dma_tag_t	dx_tag;		/* dma tag for the transfer */
     51 	int		dx_ocr;		/* direction */
     52 	int		dx_scr;		/* SCR value */
     53 	void		*dx_device;	/* (initial) device address */
     54 #ifdef DMAC_ARRAYCHAIN
     55 	struct dmac_sg_array *dx_array;	/* DMAC array chain */
     56 	int		dx_done;
     57 #endif
     58 };
     59 
     60 /*
     61  * Struct that holds the channel status.
     62  * Embedded in the device softc for each channel.
     63  */
     64 struct dmac_channel_stat {
     65 	int			ch_channel; /* channel number */
     66 	char			ch_name[8]; /* user device name */
     67 	bus_space_handle_t	ch_bht;	/* bus_space handle */
     68 	int			ch_dcr;	/* device description */
     69 	int			ch_ocr;	/* operation size, request mode */
     70 	int			ch_normalv; /* normal interrupt vector */
     71 	int			ch_errorv; /* error interrupt vector */
     72 	dmac_intr_handler_t	ch_normal; /* normal interrupt handler */
     73 	dmac_intr_handler_t	ch_error; /* error interrupt handler */
     74 	void			*ch_normalarg;
     75 	void			*ch_errorarg;
     76 	struct dmac_dma_xfer	ch_xfer;
     77 	struct dmac_sg_array	*ch_map; /* transfer map for arraychain mode */
     78 	bus_dma_segment_t	ch_seg[1];
     79 	struct dmac_softc	*ch_softc; /* device softc link */
     80 };
     81 
     82 /*
     83  * DMAC softc
     84  */
     85 struct dmac_softc {
     86 	device_t		sc_dev;
     87 
     88 	bus_space_tag_t		sc_bst;
     89 	bus_space_handle_t	sc_bht;
     90 
     91 	struct dmac_channel_stat sc_channels[DMAC_NCHAN];
     92 };
     93 
     94 
     95 #define DMAC_ADDR	0xe84000
     96 
     97 #define DMAC_MAXSEGSZ	0xff00
     98 #define DMAC_BOUNDARY	0
     99 
    100 struct dmac_channel_stat *dmac_alloc_channel(device_t,
    101 	int,		/* ch */
    102 	const char *,	/* name */
    103 	int, dmac_intr_handler_t, void *,	/* normal handler */
    104 	int, dmac_intr_handler_t, void *,	/* error handler */
    105 	uint8_t,	/* dcr */
    106 	uint8_t		/* ocr */
    107 );
    108 int dmac_free_channel(device_t, int, void *);
    109 		/* ch, channel */
    110 struct dmac_dma_xfer *dmac_alloc_xfer(struct dmac_channel_stat *,
    111 	bus_dma_tag_t, bus_dmamap_t);
    112 int dmac_load_xfer(struct dmac_softc *, struct dmac_dma_xfer *);
    113 
    114 int dmac_start_xfer(struct dmac_softc *, struct dmac_dma_xfer *);
    115 int dmac_start_xfer_offset(struct dmac_softc *, struct dmac_dma_xfer *,
    116 	u_int, u_int);
    117 int dmac_abort_xfer(struct dmac_softc *, struct dmac_dma_xfer *);
    118 /* Compatibility function: alloc, fill defaults, load */
    119 struct dmac_dma_xfer *dmac_prepare_xfer(struct dmac_channel_stat *,
    120 	bus_dma_tag_t, bus_dmamap_t, int, int, void *);
    121 	/* chan, dmat, map, dir, sequence, dar */
    122