| /src/sys/arch/arm/ti/ |
| omap3_prm.c | 67 int clocks; local
74 clocks = of_find_firstchild_byname(phandle, "clocks");
75 if (clocks > 0)
76 fdt_add_bus(self, clocks, faa);
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| omap3_cm.c | 194 int clocks; local
211 clocks = of_find_firstchild_byname(sc->sc_phandle, "clocks");
212 if (clocks > 0)
213 fdt_add_bus(self, clocks, faa);
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| am3_prcm.c | 267 int clocks, child, cm_child; local
302 clocks = of_find_firstchild_byname(phandle, "clocks");
303 if (clocks > 0)
304 fdt_add_bus(self, clocks, faa);
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| omap4_prcm.c | 295 int clocks, child, cm_child; local
351 clocks = of_find_firstchild_byname(phandle, "clocks");
352 if (clocks > 0)
353 fdt_add_bus(self, clocks, faa);
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| /src/sys/arch/hpcmips/dev/ |
| mq200debug.c | 64 int clocks[4]; local
80 clocks[0] = 0;
91 clocks[1] = sc->sc_baseclock*m/n;
99 clocks[2] = sc->sc_baseclock*m/n;
105 clocks[2] = 0;
114 clocks[3] = sc->sc_baseclock*m/n;
120 clocks[3] = 0;
124 FIXEDFLOAT1000(clocks[memclock]),
127 FIXEDFLOAT1000(clocks[geclock]),
138 FIXEDFLOAT1000(clocks[rc]*10/fd_vals[fd]/sd)
[all...] |
| /src/libexec/telnetd/ |
| global.c | 96 struct clockstate clocks; variable in typeref:struct:clockstate
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| /src/sys/arch/amiga/dev/ |
| grf_cv3d.c | 212 static unsigned char clocks[]={ variable
555 mnr = clocks; /* there the vals are stored */
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| grf_cv.c | 187 static unsigned char clocks[]={ variable
605 mnr = clocks; /* there the vals are stored */
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_pm.c | 52 static const struct cg_flag_name clocks[] = { variable in typeref:struct:cg_flag_name
273 * When low is selected, the clocks are forced to the lowest power state.
277 * When high is selected, the clocks are forced to the highest power state.
292 * disabled and the clocks are set for different profiling cases. This
295 * with your results. profile_standard sets the clocks to a fixed clock
298 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
665 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
2700 * hwmon interfaces for GPU clocks:
3548 /* GPU Clocks */
3550 seq_printf(m, "GFX Clocks and Power:\n")
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_vega20_ppt.c | 933 struct pp_clock_levels_with_latency *clocks,
939 clocks->num_levels = count;
942 clocks->data[i].clocks_in_khz =
944 clocks->data[i].latency_in_us = 0;
957 struct pp_clock_levels_with_latency clocks; local
979 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
985 for (i = 0; i < clocks.num_levels; i++)
987 clocks.data[i].clocks_in_khz / 1000,
988 (clocks.data[i].clocks_in_khz == now * 10)
1000 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table)
2608 struct pp_clock_levels_with_latency clocks; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_smu10_hwmgr.c | 202 struct PP_Clocks clocks = {0}; local
205 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
207 clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
995 struct pp_clock_levels_with_latency *clocks)
1034 clocks->num_levels = 0;
1037 clocks->data[clocks->num_levels].clocks_in_khz =
1039 clocks->data[clocks->num_levels].latency_in_us = latency_required ?
1043 clocks->num_levels++
[all...] |
| amdgpu_smu8_hwmgr.c | 723 /* update minimum clocks for Stable P-State feature */
1053 struct PP_Clocks clocks = {0, 0, 0, 0}; local
1060 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ?
1066 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
1068 force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1])
1609 struct amd_pp_clocks *clocks)
1615 clocks->count = smu8_get_max_sclk_level(hwmgr);
1618 for (i = 0; i < clocks->count; i++)
1619 clocks->clock[i] = data->sys_info.display_clock[i] * 10;
1623 for (i = 0; i < clocks->count; i++
[all...] |
| amdgpu_vega12_hwmgr.c | 1716 struct pp_clock_levels_with_latency *clocks)
1731 clocks->data[i].clocks_in_khz =
1734 clocks->data[i].latency_in_us = 0;
1737 clocks->num_levels = ucount;
1749 struct pp_clock_levels_with_latency *clocks)
1763 clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;
1765 clocks->data[i].latency_in_us =
1770 clocks->num_levels = data->mclk_latency_table.count = ucount;
1776 struct pp_clock_levels_with_latency *clocks)
1792 clocks->data[i].clocks_in_khz
2096 struct pp_clock_levels_with_latency clocks; local
[all...] |
| amdgpu_vega20_hwmgr.c | 1730 "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1745 "[EnableDPMTasks] Failed to populate umdpstate clocks!",
2765 struct pp_clock_levels_with_latency *clocks)
2775 clocks->num_levels = count;
2778 clocks->data[i].clocks_in_khz =
2780 clocks->data[i].latency_in_us = 0;
2793 struct pp_clock_levels_with_latency *clocks)
2803 clocks->num_levels = data->mclk_latency_table.count = count;
2806 clocks->data[i].clocks_in_khz =
2809 clocks->data[i].latency_in_us
3272 struct pp_clock_levels_with_latency clocks; local
[all...] |
| /src/usr.bin/telnet/ |
| telnet.c | 155 * The following are some clocks used to decide how to interpret
159 Clocks clocks; variable
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| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_sdvo.c | 729 struct intel_sdvo_pixel_clock_range clocks; local
731 BUILD_BUG_ON(sizeof(clocks) != 4);
734 &clocks, sizeof(clocks)))
738 *clock_min = clocks.min * 10;
739 *clock_max = clocks.max * 10;
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