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    Searched defs:cp_int_cntl (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v6_0.c 3243 u32 cp_int_cntl; local
3247 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3248 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3249 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3252 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3253 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3254 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3265 u32 cp_int_cntl; local
3269 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3270 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK
3306 u32 cp_int_cntl; local
3331 u32 cp_int_cntl; local
    [all...]
amdgpu_gfx_v10_0.c 4815 uint32_t cp_int_cntl, cp_int_cntl_reg; local
4836 cp_int_cntl = RREG32(cp_int_cntl_reg);
4837 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4839 WREG32(cp_int_cntl_reg, cp_int_cntl);
4842 cp_int_cntl = RREG32(cp_int_cntl_reg);
4843 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4845 WREG32(cp_int_cntl_reg, cp_int_cntl);
amdgpu_gfx_v7_0.c 4714 u32 cp_int_cntl; local
4718 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4719 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4720 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4723 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4724 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4725 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4788 u32 cp_int_cntl; local
4792 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4793 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK
4813 u32 cp_int_cntl; local
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_r600.c 3658 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3799 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; local
3857 cp_int_cntl |= RB_INT_ENABLE;
3858 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3909 WREG32(CP_INT_CNTL, cp_int_cntl);
radeon_evergreen.c 222 int ring, u32 cp_int_cntl);
4476 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
4499 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; local
4530 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
4543 cp_int_cntl |= RB_INT_ENABLE;
4544 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
4567 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
4571 WREG32(CP_INT_CNTL, cp_int_cntl);
radeon_si.c 6060 u32 cp_int_cntl; local
6078 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
6090 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
6110 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
radeon_cik.c 7045 u32 cp_int_cntl; local
7065 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
7067 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
7091 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
7245 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);

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