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  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv730_dpm.c 49 struct atom_clock_dividers dividers; local in function:rv730_populate_sclk_value
62 engine_clock, false, &dividers);
66 reference_divider = 1 + dividers.ref_div;
68 if (dividers.enable_post_div)
69 post_divider = ((dividers.post_div >> 4) & 0xf) +
70 (dividers.post_div & 0xf) + 2;
79 if (dividers.enable_post_div)
84 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
85 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
86 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf)
135 struct atom_clock_dividers dividers; local in function:rv730_populate_mclk_value
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radeon_rv740_dpm.c 129 struct atom_clock_dividers dividers; local in function:rv740_populate_sclk_value
142 engine_clock, false, &dividers);
146 reference_divider = 1 + dividers.ref_div;
148 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
153 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
154 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
165 u32 vco_freq = engine_clock * dividers.post_div;
204 struct atom_clock_dividers dividers; local in function:rv740_populate_mclk_value
210 memory_clock, false, &dividers);
214 ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div)
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radeon_ni.c 2731 struct atom_clock_dividers dividers; local in function:tn_set_vce_clocks
2735 ecclk, false, &dividers);
2747 WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));
radeon_rs780_dpm.c 83 struct atom_clock_dividers dividers; local in function:rs780_initialize_dpm_power_state
88 default_state->sclk_low, false, &dividers);
92 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
93 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
94 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
96 if (dividers.enable_post_div)
1041 struct atom_clock_dividers dividers; local in function:rs780_dpm_force_performance_level
1052 ps->sclk_high, false, &dividers);
1056 rs780_force_fbdiv(rdev, dividers.fb_div);
1059 ps->sclk_low, false, &dividers);
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radeon_cypress_dpm.c 500 struct atom_clock_dividers dividers; local in function:cypress_populate_mclk_value
507 memory_clock, strobe_mode, &dividers);
515 dividers.post_div = 1;
518 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
525 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
526 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
527 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
528 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
531 if (dividers.vco_mode)
542 mpll_dq_func_cntl |= CLKR(dividers.ref_div)
2031 struct atom_clock_dividers dividers; local in function:cypress_dpm_init
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radeon_btc_dpm.c 2561 struct atom_clock_dividers dividers; local in function:btc_dpm_init
2613 0, false, &dividers);
2615 pi->ref_div = dividers.ref_div + 1;
radeon_kv_dpm.c 543 struct atom_clock_dividers dividers; local in function:kv_set_divider_value
547 sclk, false, &dividers);
551 pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
828 struct atom_clock_dividers dividers; local in function:kv_populate_uvd_table
851 table->entries[i].vclk, false, &dividers);
854 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
857 table->entries[i].dclk, false, &dividers);
860 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
901 struct atom_clock_dividers dividers; local in function:kv_populate_vce_table
919 table->entries[i].evclk, false, &dividers);
962 struct atom_clock_dividers dividers; local in function:kv_populate_samu_table
1028 struct atom_clock_dividers dividers; local in function:kv_populate_acp_table
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radeon_rv6xx_dpm.c 147 struct atom_clock_dividers dividers; local in function:rv6xx_convert_clock_to_stepping
150 clock, false, &dividers);
154 if (dividers.enable_post_div)
155 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4);
531 struct atom_clock_dividers *dividers,
534 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) /
535 (dividers->ref_div + 1);
558 struct atom_clock_dividers dividers; local in function:rv6xx_program_engine_spread_spectrum
565 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers) == 0)
605 struct atom_clock_dividers dividers; local in function:rv6xx_program_mclk_stepping_entry
661 struct atom_clock_dividers dividers; local in function:rv6xx_program_mclk_spread_spectrum_parameters
1940 struct atom_clock_dividers dividers; local in function:rv6xx_dpm_init
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radeon_rv770_dpm.c 325 struct atom_clock_dividers *dividers,
337 post_divider = dividers->post_div;
338 reference_divider = dividers->ref_div;
407 struct atom_clock_dividers dividers; local in function:rv770_populate_mclk_value
415 memory_clock, false, &dividers);
419 if ((dividers.ref_div < 1) || (dividers.ref_div > 5))
424 &dividers, &clkf, &clkfrac);
426 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk);
437 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1])
493 struct atom_clock_dividers dividers; local in function:rv770_populate_sclk_value
2351 struct atom_clock_dividers dividers; local in function:rv770_dpm_init
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radeon_sumo_dpm.c 556 struct atom_clock_dividers dividers; local in function:sumo_program_power_level
560 pl->sclk, false, &dividers);
564 sumo_set_divider_value(rdev, index, dividers.post_div);
791 struct atom_clock_dividers dividers; local in function:sumo_program_acpi_power_level
796 false, &dividers);
800 WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
radeon_trinity_dpm.c 372 struct atom_clock_dividers dividers; local in function:trinity_gfx_powergating_initialize
379 25000, false, &dividers);
387 value |= PDS_DIV(dividers.post_div);
591 struct atom_clock_dividers dividers; local in function:trinity_set_divider_value
597 sclk, false, &dividers);
603 value |= CLK_DIVIDER(dividers.post_div);
607 sclk/2, false, &dividers);
613 value |= PD_SCLK_DIVIDER(dividers.post_div);
radeon_ni_dpm.c 2008 struct atom_clock_dividers dividers; local in function:ni_calculate_sclk_params
2022 engine_clock, false, &dividers);
2026 reference_divider = 1 + dividers.ref_div;
2029 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
2034 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
2035 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
2046 u32 vco_freq = engine_clock * dividers.post_div;
2181 struct atom_clock_dividers dividers; local in function:ni_populate_mclk_value
2188 memory_clock, strobe_mode, &dividers);
2196 dividers.post_div = 1
4055 struct atom_clock_dividers dividers; local in function:ni_dpm_init
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  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu8_hwmgr.c 446 pp_atomctrl_clock_dividers_kong dividers; local in function:smu8_upload_pptable_to_smu
491 &dividers);
494 (uint8_t)dividers.pll_post_divider;
508 &dividers);
511 (uint8_t)dividers.pll_post_divider;
522 &dividers);
525 (uint8_t)dividers.pll_post_divider;
534 &dividers);
537 (uint8_t)dividers.pll_post_divider;
548 &dividers);
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amdgpu_vega10_hwmgr.c 1500 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local in function:vega10_populate_single_lclk_level
1505 lclock, &dividers),
1509 *curr_lclk_did = dividers.ulDid;
1568 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local in function:vega10_populate_single_gfx_level
1597 gfx_clock, &dividers),
1603 cpu_to_le32(dividers.ulPll_fb_mult);
1605 current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
1607 cpu_to_le32(dividers.ulPll_ss_fbsmult);
1609 cpu_to_le16(dividers.usPll_ss_slew_frac);
1610 current_gfxclk_level->Did = (uint8_t)(dividers.ulDid)
1633 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local in function:vega10_populate_single_soc_level
1769 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local in function:vega10_populate_single_memory_level
1940 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local in function:vega10_populate_single_eclock_level
1993 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local in function:vega10_populate_single_vclock_level
2009 struct pp_atomfwctrl_clock_dividers_soc15 dividers; local in function:vega10_populate_single_dclock_level
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  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_vegam_smumgr.c 726 struct pp_atomctrl_clock_dividers_ai dividers; local in function:vegam_calculate_sclk_params
734 /* get the engine clock dividers for this clock value */
735 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
737 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
738 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
739 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
740 sclk_setting->PllRange = dividers.ucSclkPllRange;
742 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
744 sclk_setting->SSc_En = dividers.ucSscEnable;
745 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int
1201 struct pp_atomctrl_clock_dividers_vi dividers; local in function:vegam_populate_smc_vce_level
1314 struct pp_atomctrl_clock_dividers_vi dividers; local in function:vegam_populate_smc_uvd_level
1932 pp_atomctrl_clock_dividers_vi dividers; local in function:vegam_init_smc_table
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amdgpu_ci_smumgr.c 304 struct pp_atomctrl_clock_dividers_vi dividers; local in function:ci_calculate_sclk_params
315 /* get the engine clock dividers for this clock value */
316 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);
319 "Error retrieving Engine Clock dividers from VBIOS.",
324 ref_divider = 1 + dividers.uc_pll_ref_div;
327 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
331 SPLL_REF_DIV, dividers.uc_pll_ref_div);
333 SPLL_PDIV_A, dividers.uc_pll_post_div);
346 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
369 sclk->SclkDid = (uint8_t)dividers.pll_post_divider
1385 struct pp_atomctrl_clock_dividers_vi dividers; local in function:ci_populate_smc_acpi_level
1526 struct pp_atomctrl_clock_dividers_vi dividers; local in function:ci_populate_smc_uvd_level
1567 struct pp_atomctrl_clock_dividers_vi dividers; local in function:ci_populate_smc_vce_level
1599 struct pp_atomctrl_clock_dividers_vi dividers; local in function:ci_populate_smc_acp_level
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amdgpu_fiji_smumgr.c 866 struct pp_atomctrl_clock_dividers_vi dividers; local in function:fiji_calculate_sclk_params
877 /* get the engine clock dividers for this clock value */
878 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);
881 "Error retrieving Engine Clock dividers from VBIOS.",
886 ref_divider = 1 + dividers.uc_pll_ref_div;
889 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
893 SPLL_REF_DIV, dividers.uc_pll_ref_div);
895 SPLL_PDIV_A, dividers.uc_pll_post_div);
909 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
938 sclk->SclkDid = (uint8_t)dividers.pll_post_divider
1310 struct pp_atomctrl_clock_dividers_vi dividers; local in function:fiji_populate_smc_acpi_level
1430 struct pp_atomctrl_clock_dividers_vi dividers; local in function:fiji_populate_smc_vce_level
1469 struct pp_atomctrl_clock_dividers_vi dividers; local in function:fiji_populate_smc_acp_level
1565 struct pp_atomctrl_clock_dividers_vi dividers; local in function:fiji_populate_smc_uvd_level
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amdgpu_iceland_smumgr.c 804 pp_atomctrl_clock_dividers_vi dividers; local in function:iceland_calculate_sclk_params
815 /* get the engine clock dividers for this clock value*/
816 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);
819 "Error retrieving Engine Clock dividers from VBIOS.", return result);
824 reference_divider = 1 + dividers.uc_pll_ref_div;
827 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
831 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
833 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
847 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
873 sclk->SclkDid = (uint8_t)dividers.pll_post_divider
1432 struct pp_atomctrl_clock_dividers_vi dividers; local in function:iceland_populate_smc_acpi_level
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amdgpu_polaris10_smumgr.c 851 struct pp_atomctrl_clock_dividers_ai dividers; local in function:polaris10_calculate_sclk_params
859 /* get the engine clock dividers for this clock value */
860 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
862 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
863 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
864 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
865 sclk_setting->PllRange = dividers.ucSclkPllRange;
867 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
869 sclk_setting->SSc_En = dividers.ucSscEnable;
870 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int
1296 struct pp_atomctrl_clock_dividers_vi dividers; local in function:polaris10_populate_smc_vce_level
1402 struct pp_atomctrl_clock_dividers_vi dividers; local in function:polaris10_populate_smc_uvd_level
1836 pp_atomctrl_clock_dividers_vi dividers; local in function:polaris10_init_smc_table
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amdgpu_tonga_smumgr.c 547 pp_atomctrl_clock_dividers_vi dividers; local in function:tonga_calculate_sclk_params
558 /* get the engine clock dividers for this clock value*/
559 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);
562 "Error retrieving Engine Clock dividers from VBIOS.", return result);
567 reference_divider = 1 + dividers.uc_pll_ref_div;
570 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
574 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
576 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
590 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
616 sclk->SclkDid = (uint8_t)dividers.pll_post_divider
1185 struct pp_atomctrl_clock_dividers_vi dividers; local in function:tonga_populate_smc_acpi_level
1318 pp_atomctrl_clock_dividers_vi dividers; local in function:tonga_populate_smc_uvd_level
1378 pp_atomctrl_clock_dividers_vi dividers; local in function:tonga_populate_smc_vce_level
1423 pp_atomctrl_clock_dividers_vi dividers; local in function:tonga_populate_smc_acp_level
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  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik.c 1387 struct atom_clock_dividers dividers; local in function:cik_set_uvd_clock
1392 clock, false, &dividers);
1399 tmp |= dividers.post_divider;
1428 struct atom_clock_dividers dividers; local in function:cik_set_vce_clocks
1433 ecclk, false, &dividers);
1448 tmp |= dividers.post_divider;
amdgpu_vi.c 794 struct atom_clock_dividers dividers; local in function:vi_set_uvd_clock
799 clock, false, &dividers);
810 tmp |= dividers.post_divider;
864 struct atom_clock_dividers dividers; local in function:vi_set_vce_clocks
885 ecclk, false, &dividers);
900 tmp |= dividers.post_divider;
amdgpu_kv_dpm.c 670 struct atom_clock_dividers dividers; local in function:kv_set_divider_value
674 sclk, false, &dividers);
678 pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
911 struct atom_clock_dividers dividers; local in function:kv_populate_uvd_table
934 table->entries[i].vclk, false, &dividers);
937 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
940 table->entries[i].dclk, false, &dividers);
943 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
984 struct atom_clock_dividers dividers; local in function:kv_populate_vce_table
1002 table->entries[i].evclk, false, &dividers);
1045 struct atom_clock_dividers dividers; local in function:kv_populate_samu_table
1111 struct atom_clock_dividers dividers; local in function:kv_populate_acp_table
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  /src/sys/external/bsd/drm2/dist/drm/amd/display/modules/color/
amdgpu_color_gamma.c 295 struct dividers { struct
1118 struct dividers dividers)
1154 dividers.divider1);
1156 dividers.divider1);
1158 dividers.divider1);
1163 dividers.divider2);
1165 dividers.divider2);
1167 dividers.divider2);
1172 dividers.divider3)
1734 struct dividers dividers; local in function:calculate_user_regamma_ramp
1794 struct dividers dividers; local in function:mod_color_calculate_degamma_params
2010 struct dividers dividers; local in function:mod_color_calculate_regamma_params
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  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.c 1176 /* even dividers */
1314 } dividers[] = { local in function:skl_ddi_calculate_wrpll
1324 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1326 for (i = 0; i < dividers[d].n_dividers; i++) {
1327 unsigned int p = dividers[d].list[i];
1335 * Skip the remaining dividers if we're sure to
1458 DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
1770 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
2182 /* even dividers */
2290 static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16 local in function:cnl_ddi_calculate_wrpll
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