1 /* $NetBSD: bus_dma_defs.h,v 1.6 2022/01/22 15:10:31 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #ifndef _MIPS_BUS_DMA_DEFS_H_ 61 #define _MIPS_BUS_DMA_DEFS_H_ 62 63 #include <sys/types.h> 64 65 #ifdef _KERNEL 66 /* 67 * Bus DMA methods. 68 */ 69 70 /* 71 * Flags used in various bus DMA methods. 72 */ 73 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 74 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 75 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 76 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 77 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 78 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 79 #define BUS_DMA_BUS2 0x020 80 #define BUS_DMA_BUS3 0x040 81 #define BUS_DMA_BUS4 0x080 82 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 83 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 84 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 85 #define BUS_DMA_PREFETCHABLE 0x800 /* hint: map non-cached but allow 86 * things like write combining */ 87 88 /* 89 * Private flags stored in the DMA map. 90 */ 91 #define _BUS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */ 92 93 /* Forwards needed by prototypes below. */ 94 struct mbuf; 95 struct uio; 96 97 /* 98 * Operations performed by bus_dmamap_sync(). 99 */ 100 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 101 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 102 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 103 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 104 105 typedef struct mips_bus_dma_tag *bus_dma_tag_t; 106 typedef struct mips_bus_dmamap *bus_dmamap_t; 107 108 /* 109 * bus_dma_segment_t 110 * 111 * Describes a single contiguous DMA transaction. Values 112 * are suitable for programming into DMA registers. 113 */ 114 struct mips_bus_dma_segment { 115 bus_addr_t ds_addr; /* DMA address */ 116 bus_size_t ds_len; /* length of transfer */ 117 register_t _ds_vaddr; /* virtual address, 0 if invalid */ 118 }; 119 typedef struct mips_bus_dma_segment bus_dma_segment_t; 120 121 /* 122 * DMA mapping methods. 123 */ 124 struct mips_bus_dmamap_ops { 125 int (*dmamap_create)(bus_dma_tag_t, bus_size_t, int, 126 bus_size_t, bus_size_t, int, bus_dmamap_t *); 127 void (*dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 128 int (*dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 129 bus_size_t, struct proc *, int); 130 int (*dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 131 struct mbuf *, int); 132 int (*dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 133 struct uio *, int); 134 int (*dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 135 bus_dma_segment_t *, int, bus_size_t, int); 136 void (*dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 137 void (*dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 138 bus_addr_t, bus_size_t, int); 139 }; 140 141 /* 142 * DMA memory utility functions. 143 */ 144 struct mips_bus_dmamem_ops { 145 int (*dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 146 bus_size_t, bus_dma_segment_t *, int, int *, int); 147 void (*dmamem_free)(bus_dma_tag_t, 148 bus_dma_segment_t *, int); 149 int (*dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 150 int, size_t, void **, int); 151 void (*dmamem_unmap)(bus_dma_tag_t, void *, size_t); 152 paddr_t (*dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 153 int, off_t, int, int); 154 }; 155 156 /* 157 * DMA tag utility functions. 158 */ 159 struct mips_bus_dmatag_ops { 160 int (*dmatag_subregion)(bus_dma_tag_t, bus_addr_t, bus_addr_t, 161 bus_dma_tag_t *, int); 162 void (*dmatag_destroy)(bus_dma_tag_t); 163 }; 164 165 /* 166 * bus_dma_tag_t 167 * 168 * A machine-dependent opaque type describing the implementation of 169 * DMA for a given bus. 170 */ 171 struct mips_bus_dma_tag { 172 void *_cookie; /* cookie used in the guts */ 173 174 bus_addr_t _wbase; /* DMA window base */ 175 int _tag_needs_free; /* number of references (maybe 0) */ 176 bus_addr_t _bounce_thresh; 177 bus_addr_t _bounce_alloc_lo; /* physical base of the window */ 178 bus_addr_t _bounce_alloc_hi; /* physical limit of the windows */ 179 int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *); 180 181 struct mips_bus_dmamap_ops _dmamap_ops; 182 struct mips_bus_dmamem_ops _dmamem_ops; 183 struct mips_bus_dmatag_ops _dmatag_ops; 184 }; 185 186 /* 187 * bus_dmamap_t 188 * 189 * Describes a DMA mapping. 190 */ 191 struct mips_bus_dmamap { 192 /* 193 * PRIVATE MEMBERS: not for use my machine-independent code. 194 */ 195 bus_size_t _dm_size; /* largest DMA transfer mappable */ 196 int _dm_segcnt; /* number of segs this map can map */ 197 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 198 bus_size_t _dm_boundary; /* don't cross this */ 199 bus_addr_t _dm_bounce_thresh; /* bounce threshold; see tag */ 200 int _dm_flags; /* misc. flags */ 201 struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */ 202 203 /* 204 * Private cookie to be used by the DMA back-end. 205 */ 206 void *_dm_cookie; 207 208 /* 209 * PUBLIC MEMBERS: these are used by machine-independent code. 210 */ 211 bus_size_t dm_maxsegsz; /* largest possible segment */ 212 bus_size_t dm_mapsize; /* size of the mapping */ 213 int dm_nsegs; /* # valid segments in mapping */ 214 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 215 }; 216 217 #ifdef _MIPS_BUS_DMA_PRIVATE 218 #define _BUS_AVAIL_END (pmap_limits.avail_end - 1) 219 /* 220 * Cookie used for bounce buffers. A pointer to one of these it stashed in 221 * the DMA map. 222 */ 223 struct mips_bus_dma_cookie { 224 int id_flags; /* flags; see below */ 225 226 /* 227 * Information about the original buffer used during 228 * DMA map syncs. Note that origibuflen is only used 229 * for ID_BUFTYPE_LINEAR. 230 */ 231 union { 232 void *un_origbuf; /* pointer to orig buffer if 233 bouncing */ 234 char *un_linearbuf; 235 struct mbuf *un_mbuf; 236 struct uio *un_uio; 237 } id_origbuf_un; 238 #define id_origbuf id_origbuf_un.un_origbuf 239 #define id_origlinearbuf id_origbuf_un.un_linearbuf 240 #define id_origmbuf id_origbuf_un.un_mbuf 241 #define id_origuio id_origbuf_un.un_uio 242 bus_size_t id_origbuflen; /* ...and size */ 243 int id_buftype; /* type of buffer */ 244 245 void *id_bouncebuf; /* pointer to the bounce buffer */ 246 bus_size_t id_bouncebuflen; /* ...and size */ 247 int id_nbouncesegs; /* number of valid bounce segs */ 248 bus_dma_segment_t id_bouncesegs[0]; /* array of bounce buffer 249 physical memory segments */ 250 }; 251 252 /* id_flags */ 253 #endif /* _MIPS_BUS_DMA_PRIVATE */ 254 #define _BUS_DMA_MIGHT_NEED_BOUNCE 0x01 /* may need bounce buffers */ 255 #ifdef _MIPS_BUS_DMA_PRIVATE 256 #define _BUS_DMA_HAS_BOUNCE 0x02 /* has bounce buffers */ 257 #define _BUS_DMA_IS_BOUNCING 0x04 /* is bouncing current xfer */ 258 259 /* id_buftype */ 260 #define _BUS_DMA_BUFTYPE_INVALID 0 261 #define _BUS_DMA_BUFTYPE_LINEAR 1 262 #define _BUS_DMA_BUFTYPE_MBUF 2 263 #define _BUS_DMA_BUFTYPE_UIO 3 264 #define _BUS_DMA_BUFTYPE_RAW 4 265 266 extern const struct mips_bus_dmamap_ops mips_bus_dmamap_ops; 267 extern const struct mips_bus_dmamem_ops mips_bus_dmamem_ops; 268 extern const struct mips_bus_dmatag_ops mips_bus_dmatag_ops; 269 270 #define _BUS_DMAMAP_OPS_INITIALIZER { \ 271 .dmamap_create = _bus_dmamap_create, \ 272 .dmamap_destroy = _bus_dmamap_destroy, \ 273 .dmamap_load = _bus_dmamap_load, \ 274 .dmamap_load_mbuf = _bus_dmamap_load_mbuf, \ 275 .dmamap_load_uio = _bus_dmamap_load_uio, \ 276 .dmamap_load_raw = _bus_dmamap_load_raw, \ 277 .dmamap_unload = _bus_dmamap_unload, \ 278 .dmamap_sync = _bus_dmamap_sync, \ 279 } 280 281 #define _BUS_DMAMEM_OPS_INITIALIZER { \ 282 .dmamem_alloc = _bus_dmamem_alloc, \ 283 .dmamem_free = _bus_dmamem_free, \ 284 .dmamem_map = _bus_dmamem_map, \ 285 .dmamem_unmap = _bus_dmamem_unmap, \ 286 .dmamem_mmap = _bus_dmamem_mmap, \ 287 } 288 289 #define _BUS_DMATAG_OPS_INITIALIZER { \ 290 .dmatag_subregion = _bus_dmatag_subregion, \ 291 .dmatag_destroy = _bus_dmatag_destroy, \ 292 } 293 #endif /* _MIPS_BUS_DMA_PRIVATE */ 294 295 #endif /* _KERNEL */ 296 297 #endif /* _MIPS_BUS_DMA_DEFS_H_ */ 298
Indexes created Mon Sep 22 10:09:38 GMT 2025