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    Searched defs:dpp (Results 1 - 18 of 18) sorted by relevancy

  /src/lib/libc/resolv/
res_mkquery.c 125 u_char *dnptrs[20], **dpp, **lastdnptr; local
149 dpp = dnptrs;
150 *dpp++ = buf;
151 *dpp++ = NULL;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_dpp.c 47 dpp->tf_regs->reg
50 dpp->base.ctx
54 dpp->tf_shift->field_name, dpp->tf_mask->field_name
99 void dpp_read_state(struct dpp *dpp_base,
102 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
128 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
138 struct dpp *dpp,
151 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &
210 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
226 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
282 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
307 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
433 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
456 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
495 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
508 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
    [all...]
amdgpu_dcn10_hw_sequencer_debug.c 347 struct dpp *dpp = pool->dpps[i]; local
350 dpp->funcs->dpp_read_state(dpp, &s);
357 dpp->inst, s.igam_input_format,
395 chars_printed = snprintf_count(pBuf, remaining_buffer, "instance,opp,dpp,mpccbot,mode,alpha_mode,premult,overlap_only,idle\n");
amdgpu_dcn10_dpp_cm.c 48 dpp->tf_regs->reg
51 dpp->base.ctx
55 dpp->tf_shift->field_name, dpp->tf_mask->field_name
97 struct dcn10_dpp *dpp,
123 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
124 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
125 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
126 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
134 dpp->base.ctx
169 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
248 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
318 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
326 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
338 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
359 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
373 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
402 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
431 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
505 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
526 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
555 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
582 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
592 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
602 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
632 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
647 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
670 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
712 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
739 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
770 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
818 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
    [all...]
amdgpu_dcn10_dpp_dscl.c 48 dpp->tf_regs->reg
51 dpp->base.ctx
55 dpp->tf_shift->field_name, dpp->tf_mask->field_name
94 struct dcn10_dpp *dpp,
122 struct dcn10_dpp *dpp, const struct scaler_data *data)
173 struct dpp *dpp_base,
207 struct dcn10_dpp *dpp,
212 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
264 struct dcn10_dpp *dpp,
534 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
673 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local
    [all...]
amdgpu_dcn10_hw_sequencer.c 286 DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode"
290 struct dpp *dpp = pool->dpps[i]; local
293 dpp->funcs->dpp_read_state(dpp, &s);
300 dpp->inst,
330 DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n");
1034 int dpp_id = pipe_ctx->plane_res.dpp->inst;
1061 struct dpp *dpp,
1087 struct dpp *dpp = pipe_ctx->plane_res.dpp; local
1186 struct dpp *dpp = dc->res_pool->dpps[i]; local
1540 struct dpp *dpp = pipe_ctx->plane_res.dpp; local
2240 struct dpp *dpp = pipe_ctx->plane_res.dpp; local
2950 struct dpp *dpp = pipe_ctx->plane_res.dpp; local
    [all...]
amdgpu_dcn10_resource.c 616 static void dcn10_dpp_destroy(struct dpp **dpp)
618 kfree(TO_DCN10_DPP(*dpp));
619 *dpp = NULL;
622 static struct dpp *dcn10_dpp_create(
626 struct dcn10_dpp *dpp = local
629 if (!dpp)
632 dpp1_construct(dpp, ctx, inst,
634 return &dpp->base;
1156 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_dpp.c 47 dpp->tf_regs->reg
50 dpp->base.ctx
54 dpp->tf_shift->field_name, dpp->tf_mask->field_name
56 void dpp20_read_state(struct dpp *dpp_base,
59 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
81 struct dpp *dpp_base,
84 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
96 struct dpp *dpp_base,
101 struct dpp *dpp_base
108 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
258 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
329 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
353 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
    [all...]
amdgpu_dcn20_dpp_cm.c 42 dpp->tf_regs->reg
48 dpp->base.ctx
52 dpp->tf_shift->field_name, dpp->tf_mask->field_name
56 struct dpp *dpp_base)
58 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
70 struct dpp *dpp_base,
75 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
91 struct dpp *dpp_base,
98 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base) local
143 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
222 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
248 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
319 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
330 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
345 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
395 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
423 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
450 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
477 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
516 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
543 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
569 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
585 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
735 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
888 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
924 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
970 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
989 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
1005 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
1039 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
1058 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
1149 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local
    [all...]
amdgpu_dcn20_hwseq.c 563 struct dpp *dpp = pipe_ctx->plane_res.dpp; local
577 dpp->funcs->dpp_dppclk_control(dpp, false, false);
582 pipe_ctx->plane_res.dpp,
782 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
804 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
1317 struct dpp *dpp = pipe_ctx->plane_res.dpp; local
2334 struct dpp *dpp = res_pool->dpps[i]; local
2354 struct dpp *dpp = dc->res_pool->dpps[i]; local
    [all...]
amdgpu_dcn20_resource.c 969 void dcn20_dpp_destroy(struct dpp **dpp)
971 kfree(TO_DCN20_DPP(*dpp));
972 *dpp = NULL;
975 struct dpp *dcn20_dpp_create(
979 struct dcn20_dpp *dpp = local
982 if (!dpp)
985 if (dpp2_construct(dpp, ctx, inst,
987 return &dpp->base;
990 kfree(dpp);
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
dpp.h 1 /* $NetBSD: dpp.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */
34 struct dpp { struct
127 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
131 struct dpp *dpp_base,
134 void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);
136 void (*dpp_reset)(struct dpp *dpp);
138 void (*dpp_set_scaler)(struct dpp *dpp,
    [all...]
opp.h 202 int dpp[MAX_PIPES]; member in struct:mpc_tree_cfg
  /src/sys/kern/
uipc_domain.c 105 struct domain * const * dpp; local
115 __link_set_foreach(dpp, domains) {
116 if (*dpp == &domain_dummy)
118 if ((*dpp)->dom_family == PF_ROUTE)
119 rt_domain = *dpp;
121 domain_attach(*dpp);
  /src/lib/libresolv/
res_mkupdate.c 97 u_char *dnptrs[20], **dpp, **lastdnptr; local
113 dpp = dnptrs;
114 *dpp++ = buf;
115 *dpp++ = NULL;
  /src/sys/arch/i386/stand/efiboot/
eficons.c 869 EFI_DEV_PATH_PTR dpp; local
908 dpp = (EFI_DEV_PATH_PTR)dp;
909 if (dpp.Acpi->HID == EISA_PNP_ID(0x0501)) {
910 unit = dpp.Acpi->UID;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_resource.c 691 static struct dpp *dcn21_dpp_create(
695 struct dcn20_dpp *dpp = local
698 if (!dpp)
701 if (dpp2_construct(dpp, ctx, inst,
703 return &dpp->base;
706 kfree(dpp);
1798 /* mem input -> ipp -> dpp -> opp -> TG */
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 87 #include "dpp.h"
165 struct dpp *dpps[MAX_PIPES];
253 struct dpp *dpp; member in struct:plane_resource

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