| /src/lib/libc/resolv/ |
| res_mkquery.c | 125 u_char *dnptrs[20], **dpp, **lastdnptr; local in function:res_nmkquery
149 dpp = dnptrs;
150 *dpp++ = buf;
151 *dpp++ = NULL;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp.c | 47 dpp->tf_regs->reg
50 dpp->base.ctx
54 dpp->tf_shift->field_name, dpp->tf_mask->field_name
99 void dpp_read_state(struct dpp *dpp_base,
102 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp_read_state
128 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
138 struct dpp *dpp,
151 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &
210 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp_reset
226 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_cm_set_regamma_pwl
282 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_set_degamma_format_float
307 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_cnv_setup
433 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_set_cursor_attributes
456 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_set_cursor_position
495 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_cnv_set_optional_cursor_attributes
508 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_dppclk_control
[all...] |
| amdgpu_dcn10_hw_sequencer_debug.c | 347 struct dpp *dpp = pool->dpps[i]; local in function:dcn10_get_cm_states
350 dpp->funcs->dpp_read_state(dpp, &s);
357 dpp->inst, s.igam_input_format,
395 chars_printed = snprintf_count(pBuf, remaining_buffer, "instance,opp,dpp,mpccbot,mode,alpha_mode,premult,overlap_only,idle\n");
|
| amdgpu_dcn10_dpp_cm.c | 48 dpp->tf_regs->reg
51 dpp->base.ctx
55 dpp->tf_shift->field_name, dpp->tf_mask->field_name
97 struct dcn10_dpp *dpp,
123 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
124 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
125 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
126 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
134 dpp->base.ctx
169 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_cm_set_gamut_remap
248 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_cm_set_output_csc_default
318 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_cm_set_output_csc_adjustment
326 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_cm_power_on_regamma_lut
338 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_cm_program_regamma_lut
359 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_cm_configure_regamma_lut
373 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_cm_program_regamma_luta_settings
402 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_cm_program_regamma_lutb_settings
431 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_program_input_csc
505 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_program_bias_and_scale
526 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_program_degamma_lutb_settings
555 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_program_degamma_luta_settings
582 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_power_on_degamma_lut
592 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_enable_cm_block
602 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_set_degamma
632 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_degamma_ram_select
647 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_degamma_ram_inuse
670 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_program_degamma_lut
712 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_full_bypass
739 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_ingamma_ram_inuse
770 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_program_input_lut
818 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_set_hdr_multiplier
[all...] |
| amdgpu_dcn10_dpp_dscl.c | 48 dpp->tf_regs->reg
51 dpp->base.ctx
55 dpp->tf_shift->field_name, dpp->tf_mask->field_name
94 struct dcn10_dpp *dpp,
122 struct dcn10_dpp *dpp, const struct scaler_data *data)
173 struct dpp *dpp_base,
207 struct dcn10_dpp *dpp,
212 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
264 struct dcn10_dpp *dpp,
534 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_dscl_set_scaler_auto_scale
673 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local in function:dpp1_dscl_set_scaler_manual_scale
[all...] |
| amdgpu_dcn10_hw_sequencer.c | 286 DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode"
290 struct dpp *dpp = pool->dpps[i]; local in function:dcn10_log_hw_state
293 dpp->funcs->dpp_read_state(dpp, &s);
300 dpp->inst,
330 DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n");
1034 int dpp_id = pipe_ctx->plane_res.dpp->inst;
1061 struct dpp *dpp,
1087 struct dpp *dpp = pipe_ctx->plane_res.dpp; local in function:dcn10_plane_atomic_disable
1186 struct dpp *dpp = dc->res_pool->dpps[i]; local in function:dcn10_init_pipes
1540 struct dpp *dpp = pipe_ctx->plane_res.dpp; local in function:dcn10_set_output_transfer_func
2240 struct dpp *dpp = pipe_ctx->plane_res.dpp; local in function:dcn10_update_dchubp_dpp
2950 struct dpp *dpp = pipe_ctx->plane_res.dpp; local in function:dcn10_set_cursor_position
[all...] |
| amdgpu_dcn10_resource.c | 616 static void dcn10_dpp_destroy(struct dpp **dpp)
618 kfree(TO_DCN10_DPP(*dpp));
619 *dpp = NULL;
622 static struct dpp *dcn10_dpp_create(
626 struct dcn10_dpp *dpp = local in function:dcn10_dpp_create
629 if (!dpp)
632 dpp1_construct(dpp, ctx, inst,
634 return &dpp->base;
1156 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dpp.c | 47 dpp->tf_regs->reg
50 dpp->base.ctx
54 dpp->tf_shift->field_name, dpp->tf_mask->field_name
56 void dpp20_read_state(struct dpp *dpp_base,
59 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_read_state
81 struct dpp *dpp_base,
84 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp2_power_on_obuf
96 struct dpp *dpp_base,
101 struct dpp *dpp_base
108 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp2_cnv_setup
258 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp2_cnv_set_bias_scale
329 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp2_cnv_set_alpha_keyer
353 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp2_set_cursor_attributes
[all...] |
| amdgpu_dcn20_dpp_cm.c | 42 dpp->tf_regs->reg
48 dpp->base.ctx
52 dpp->tf_shift->field_name, dpp->tf_mask->field_name
56 struct dpp *dpp_base)
58 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp2_enable_cm_block
70 struct dpp *dpp_base,
75 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp2_degamma_ram_inuse
91 struct dpp *dpp_base,
98 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base) local in function:dpp2_program_degamma_lut
143 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp2_set_degamma
222 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp2_cm_set_gamut_remap
248 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp2_program_input_csc
319 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_power_on_blnd_lut
330 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_configure_blnd_lut
345 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_program_blnd_pwl
395 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_program_blnd_luta_settings
423 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_program_blnd_lutb_settings
450 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_get_blndgam_current
477 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_program_blnd_lut
516 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_program_shaper_lut
543 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_get_shaper_current
569 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_configure_shaper_lut
585 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_program_shaper_luta_settings
735 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_program_shaper_lutb_settings
888 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_program_shaper
924 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:get3dlut_config
970 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_set_3dlut_mode
989 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_select_3dlut_ram
1005 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_set3dlut_ram12
1039 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_set3dlut_ram10
1058 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp20_select_3dlut_ram_mask
1149 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local in function:dpp2_set_hdr_multiplier
[all...] |
| amdgpu_dcn20_hwseq.c | 563 struct dpp *dpp = pipe_ctx->plane_res.dpp; local in function:dcn20_plane_atomic_disable
577 dpp->funcs->dpp_dppclk_control(dpp, false, false);
582 pipe_ctx->plane_res.dpp,
782 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
804 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
1317 struct dpp *dpp = pipe_ctx->plane_res.dpp; local in function:dcn20_update_dchubp_dpp
2334 struct dpp *dpp = res_pool->dpps[i]; local in function:dcn20_fpga_init_hw
2354 struct dpp *dpp = dc->res_pool->dpps[i]; local in function:dcn20_fpga_init_hw
[all...] |
| amdgpu_dcn20_resource.c | 969 void dcn20_dpp_destroy(struct dpp **dpp)
971 kfree(TO_DCN20_DPP(*dpp));
972 *dpp = NULL;
975 struct dpp *dcn20_dpp_create(
979 struct dcn20_dpp *dpp = local in function:dcn20_dpp_create
982 if (!dpp)
985 if (dpp2_construct(dpp, ctx, inst,
987 return &dpp->base;
990 kfree(dpp);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| dpp.h | 1 /* $NetBSD: dpp.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */
34 struct dpp { struct
127 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
131 struct dpp *dpp_base,
134 void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);
136 void (*dpp_reset)(struct dpp *dpp);
138 void (*dpp_set_scaler)(struct dpp *dpp,
[all...] |
| opp.h | 202 int dpp[MAX_PIPES]; member in struct:mpc_tree_cfg
|
| /src/sys/kern/ |
| uipc_domain.c | 105 struct domain * const * dpp; local in function:domaininit
115 __link_set_foreach(dpp, domains) {
116 if (*dpp == &domain_dummy)
118 if ((*dpp)->dom_family == PF_ROUTE)
119 rt_domain = *dpp;
121 domain_attach(*dpp);
|
| /src/lib/libresolv/ |
| res_mkupdate.c | 97 u_char *dnptrs[20], **dpp, **lastdnptr; local in function:res_nmkupdate
113 dpp = dnptrs;
114 *dpp++ = buf;
115 *dpp++ = NULL;
|
| /src/sys/arch/i386/stand/efiboot/ |
| eficons.c | 814 EFI_DEV_PATH_PTR dpp; local in function:efi_com_probe
840 dpp = (EFI_DEV_PATH_PTR)dp;
841 if (dpp.Acpi->HID == EISA_PNP_ID(0x0501)) {
842 uid = dpp.Acpi->UID;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 691 static struct dpp *dcn21_dpp_create(
695 struct dcn20_dpp *dpp = local in function:dcn21_dpp_create
698 if (!dpp)
701 if (dpp2_construct(dpp, ctx, inst,
703 return &dpp->base;
706 kfree(dpp);
1798 /* mem input -> ipp -> dpp -> opp -> TG */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 87 #include "dpp.h"
165 struct dpp *dpps[MAX_PIPES];
253 struct dpp *dpp; member in struct:plane_resource
|
