1 /* $NetBSD: drsc.c,v 1.35 2021/08/07 16:18:41 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Ignatios Souvatzis 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * @(#)dma.c 33 */ 34 35 /* 36 * Copyright (c) 1994 Michael L. Hitch 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 * 58 * @(#)dma.c 59 */ 60 61 #include <sys/cdefs.h> 62 __KERNEL_RCSID(0, "$NetBSD: drsc.c,v 1.35 2021/08/07 16:18:41 thorpej Exp $"); 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/kernel.h> 67 #include <sys/device.h> 68 69 #include <dev/scsipi/scsi_all.h> 70 #include <dev/scsipi/scsipi_all.h> 71 #include <dev/scsipi/scsiconf.h> 72 #include <amiga/amiga/custom.h> 73 #include <amiga/amiga/cc.h> 74 #include <amiga/amiga/device.h> 75 #include <amiga/amiga/isr.h> 76 #include <amiga/dev/siopreg.h> 77 #include <amiga/dev/siopvar.h> 78 #include <amiga/amiga/drcustom.h> 79 #include <m68k/include/asm_single.h> 80 81 #include <machine/cpu.h> /* is_xxx(), */ 82 83 void drscattach(device_t, device_t, void *); 84 int drscmatch(device_t, cfdata_t, void *); 85 int drsc_dmaintr(struct siop_softc *); 86 #ifdef DEBUG 87 void drsc_dump(void); 88 #endif 89 90 #ifdef DEBUG 91 #endif 92 93 CFATTACH_DECL_NEW(drsc, sizeof(struct siop_softc), 94 drscmatch, drscattach, NULL, NULL); 95 96 static struct siop_softc *drsc_softc; 97 98 /* 99 * One of us is on every DraCo motherboard, 100 */ 101 int 102 drscmatch(device_t parent, cfdata_t cf, void *aux) 103 { 104 static int drsc_matched = 0; 105 106 /* Allow only one instance. */ 107 if (!is_draco() || !matchname(aux, "drsc") || drsc_matched) 108 return (0); 109 110 drsc_matched = 1; 111 return(1); 112 } 113 114 void 115 drscattach(device_t parent, device_t self, void *aux) 116 { 117 struct siop_softc *sc = device_private(self); 118 siop_regmap_p rp; 119 struct scsipi_adapter *adapt = &sc->sc_adapter; 120 struct scsipi_channel *chan = &sc->sc_channel; 121 122 printf("\n"); 123 124 sc->sc_dev = self; 125 sc->sc_siopp = rp = (siop_regmap_p)(DRCCADDR+PAGE_SIZE*DRSCSIPG); 126 127 /* 128 * CTEST7 = TT1 129 */ 130 sc->sc_clock_freq = 50; /* Clock = 50MHz */ 131 sc->sc_ctest7 = 0x02; 132 133 sc->sc_siop_si = softint_establish(SOFTINT_BIO, 134 (void (*)(void *))siopintr, sc); 135 136 /* 137 * Fill in the scsipi_adapter. 138 */ 139 memset(adapt, 0, sizeof(*adapt)); 140 adapt->adapt_dev = self; 141 adapt->adapt_nchannels = 1; 142 adapt->adapt_openings = 7; 143 adapt->adapt_max_periph = 1; 144 adapt->adapt_request = siop_scsipi_request; 145 adapt->adapt_minphys = siop_minphys; 146 147 /* 148 * Fill in the scsipi_channel. 149 */ 150 memset(chan, 0, sizeof(*chan)); 151 chan->chan_adapter = adapt; 152 chan->chan_bustype = &scsi_bustype; 153 chan->chan_channel = 0; 154 chan->chan_ntargets = 8; 155 chan->chan_nluns = 8; 156 chan->chan_id = 7; 157 158 siopinitialize(sc); 159 160 #if 0 161 sc->sc_isr.isr_intr = drsc_dmaintr; 162 sc->sc_isr.isr_arg = sc; 163 sc->sc_isr.isr_ipl = 4; 164 add_isr(&sc->sc_isr); 165 #else 166 drsc_softc = sc; 167 single_inst_bclr_b(*draco_intpen, DRIRQ_SCSI); 168 single_inst_bset_b(*draco_intena, DRIRQ_SCSI); 169 #endif 170 /* 171 * attach all scsi units on us 172 */ 173 config_found(self, chan, scsiprint, CFARGS_NONE); 174 } 175 176 /* 177 * Level 4 interrupt processing for the MacroSystem DraCo mainboard 178 * SCSI. Because the level 4 interrupt is above splbio, the 179 * interrupt status is saved and a softint scheduled. This way, 180 * the actual processing of the interrupt can be deferred until 181 * splbio is unblocked. 182 */ 183 184 void 185 drsc_handler(void) 186 { 187 struct siop_softc *sc = drsc_softc; 188 189 siop_regmap_p rp; 190 int istat; 191 192 if (sc->sc_flags & SIOP_INTSOFF) 193 return; /* interrupts are not active */ 194 195 rp = sc->sc_siopp; 196 istat = rp->siop_istat; 197 198 if ((istat & (SIOP_ISTAT_SIP | SIOP_ISTAT_DIP)) == 0) 199 return; 200 201 /* 202 * save interrupt status, DMA status, and SCSI status 0 203 * (may need to deal with stacked interrupts?) 204 */ 205 sc->sc_sstat0 = rp->siop_sstat0; 206 sc->sc_istat = istat; 207 sc->sc_dstat = rp->siop_dstat; 208 /* 209 * disable interrupts until the callback can process this 210 * interrupt. 211 */ 212 #ifdef DRSC_NOCALLBACK 213 (void)spl1(); 214 siopintr(sc); 215 #else 216 rp->siop_sien = 0; 217 rp->siop_dien = 0; 218 sc->sc_flags |= SIOP_INTDEFER | SIOP_INTSOFF; 219 single_inst_bclr_b(*draco_intpen, DRIRQ_SCSI); 220 #ifdef DEBUG 221 if (*draco_intpen & DRIRQ_SCSI) 222 printf("%s: intpen still 0x%x\n", device_xname(sc->sc_dev), 223 *draco_intpen); 224 #endif 225 softint_schedule(sc->sc_siop_si); 226 #endif 227 return; 228 } 229 230 #ifdef DEBUG 231 void 232 drsc_dump(void) 233 { 234 extern struct cfdriver drsc_cd; 235 struct siop_softc *sc; 236 int i; 237 238 for (i = 0; i < drsc_cd.cd_ndevs; ++i) { 239 sc = device_lookup_private(&drsc_cd, i); 240 if (sc != NULL) 241 siop_dump(sc); 242 } 243 } 244 #endif 245
Indexes created Sat Sep 20 22:09:52 GMT 2025