/src/sys/external/bsd/drm2/dist/drm/radeon/ |
radeon_clocks.c | 48 uint32_t fb_div, ref_div, post_div, sclk; local in function:radeon_legacy_get_engine_clock 50 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); 51 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; 52 fb_div <<= 1; 53 fb_div *= spll->reference_freq; 61 sclk = fb_div / ref_div; 78 uint32_t fb_div, ref_div, post_div, mclk; local in function:radeon_legacy_get_memory_clock 80 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); 81 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK 399 int fb_div, post_div; local in function:radeon_legacy_set_engine_clock [all...] |
radeon_uvd.c | 985 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; local in function:radeon_uvd_calc_upll_dividers 988 do_div(fb_div, ref_freq); 991 if (fb_div > fb_mask) 994 fb_div &= fb_mask; 1013 *optimal_fb_div = fb_div;
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radeon_rv770.c | 58 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local in function:rv770_set_uvd_clocks 78 &fb_div, &vclk_div, &dclk_div); 82 fb_div |= 1; 92 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ 103 /* set the required FB_DIV, REF_DIV, Post divder values */ 112 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), 123 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
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radeon_atombios_crtc.c | 835 u32 fb_div, 862 args.v1.usFbDiv = cpu_to_le16(fb_div); 872 args.v2.usFbDiv = cpu_to_le16(fb_div); 882 args.v3.usFbDiv = cpu_to_le16(fb_div); 899 args.v5.usFbDiv = cpu_to_le16(fb_div); 928 args.v6.usFbDiv = cpu_to_le16(fb_div); 1077 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local in function:atombios_crtc_set_pll 1109 &fb_div, &frac_fb_div, &ref_div, &post_div); 1112 &fb_div, &frac_fb_div, &ref_div, &post_div); 1115 &fb_div, &frac_fb_div, &ref_div, &post_div) [all...] |
radeon_display.c | 916 * @fb_div: resulting feedback divider 924 unsigned *fb_div, unsigned *ref_div) 931 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 934 if (*fb_div > fb_div_max) { 935 *ref_div = (*ref_div * fb_div_max)/(*fb_div); 936 *fb_div = fb_div_max; 964 unsigned fb_div_min, fb_div_max, fb_div; local in function:radeon_compute_pll_avivo 1044 ref_div_max, &fb_div, &ref_div); 1045 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1059 &fb_div, &ref_div) [all...] |
radeon_r600.c | 212 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; local in function:r600_set_uvd_clocks 241 &fb_div, &vclk_div, &dclk_div); 246 fb_div >>= 1; 248 fb_div |= 1; 264 UPLL_FB_DIV(fb_div) |
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radeon_ni_dpm.c | 2100 u32 fb_div; local in function:ni_init_smc_spll_table 2121 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2125 fb_div &= ~0x00001FFF; 2126 fb_div >>= 1; 2144 tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
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radeon_evergreen.c | 1200 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local in function:evergreen_set_uvd_clocks 1219 &fb_div, &vclk_div, &dclk_div); 1246 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); 1251 if (fb_div < 307200)
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radeon_mode.h | 594 u32 fb_div; member in union:atom_clock_dividers::__anon4e767d89010a 619 u32 fb_div; member in union:atom_mpll_param::__anon4e767d89030a
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radeon_si.c | 7013 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; local in function:si_set_uvd_clocks 7031 &fb_div, &vclk_div, &dclk_div); 7060 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); 7065 if (fb_div < 307200) 7525 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; local in function:si_set_vce_clocks 7546 &fb_div, &evclk_div, &ecclk_div); 7578 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK);
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radeon_si_dpm.c | 2857 u32 fb_div, p_div; local in function:si_init_smc_spll_table 2877 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2881 fb_div &= ~0x00001FFF; 2882 fb_div >>= 1; 2887 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2897 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
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/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
amdgpu_pll.c | 84 * @fb_div: resulting feedback divider 92 unsigned *fb_div, unsigned *ref_div) 99 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 102 if (*fb_div > fb_div_max) { 103 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 104 *fb_div = fb_div_max; 132 unsigned fb_div_min, fb_div_max, fb_div; local in function:amdgpu_pll_compute 209 ref_div_max, &fb_div, &ref_div); 210 diff = abs(target_clock - (pll->reference_freq * fb_div) / 224 &fb_div, &ref_div) [all...] |
amdgpu_atombios.h | 43 u32 fb_div; member in union:atom_clock_dividers::__anona31b85ad010a 68 u32 fb_div; member in union:atom_mpll_param::__anona31b85ad030a
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amdgpu_atombios_crtc.c | 589 u32 fb_div, 616 args.v1.usFbDiv = cpu_to_le16(fb_div); 626 args.v2.usFbDiv = cpu_to_le16(fb_div); 636 args.v3.usFbDiv = cpu_to_le16(fb_div); 653 args.v5.usFbDiv = cpu_to_le16(fb_div); 683 args.v6.usFbDiv = cpu_to_le16(fb_div); 832 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local in function:amdgpu_atombios_crtc_set_pll 861 &fb_div, &frac_fb_div, &ref_div, &post_div); 868 ref_div, fb_div, frac_fb_div, post_div, 874 u32 amount = (((fb_div * 10) + frac_fb_div) [all...] |
amdgpu_si_dpm.c | 2957 u32 fb_div, p_div; local in function:si_init_smc_spll_table 2976 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2980 fb_div &= ~0x00001FFF; 2981 fb_div >>= 1; 2986 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2996 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
amdgpu_dce_clock_source.c | 656 struct fixed31_32 fb_div; local in function:calculate_ss 676 fb_div = dc_fixpt_from_fraction( 678 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); 684 fb_div, dc_fixpt_from_fraction(ss_data->percentage,
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