1 /* $NetBSD: btreg.h,v 1.3 2005/12/11 12:23:56 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)btreg.h 8.2 (Berkeley) 1/21/94 41 */ 42 43 /* 44 * Several Sun color frame buffers use some kind of Brooktree video 45 * DAC (e.g., the Bt458, -- in any case, Brooktree make the only 46 * decent color frame buffer chips). 47 * 48 * Color map control on these is a bit funky in a SPARCstation. 49 * To update the color map one would normally do byte writes, but 50 * the hardware takes longword writes. Since there are three 51 * registers for each color map entry (R, then G, then B), we have 52 * to set color 1 with a write to address 0 (setting 0's R/G/B and 53 * color 1's R) followed by a second write to address 1 (setting 54 * color 1's G/B and color 2's R/G). Software must therefore keep 55 * a copy of the current map. 56 * 57 * The colormap address register increments automatically, so the 58 * above write is done as: 59 * 60 * bt->bt_addr = 0; 61 * bt->bt_cmap = R0G0B0R1; 62 * bt->bt_cmap = G1B1R2G2; 63 * ... 64 * 65 * Yow! 66 * 67 * Bonus complication: on the cg6, only the top 8 bits of each 32 bit 68 * register matter, even though the cg3 takes all the bits from all 69 * bytes written to it. 70 */ 71 struct bt_regs { 72 u_int bt_addr; /* map address register */ 73 u_int bt_cmap; /* colormap data register */ 74 u_int bt_ctrl; /* control register */ 75 u_int bt_omap; /* overlay (cursor) map register */ 76 }; 77 #define BT_INIT(bt, shift) do { /* whatever this means.. */ \ 78 (bt)->bt_addr = 0x06 << (shift); /* command reg */ \ 79 (bt)->bt_ctrl = 0x73 << (shift); /* overlay plane */ \ 80 (bt)->bt_addr = 0x04 << (shift); /* read mask */ \ 81 (bt)->bt_ctrl = 0xff << (shift); /* color planes */ \ 82 } while(0) 83 #define BT_UNBLANK(bt, x, shift) do { \ 84 /* restore color 0 (and R of color 1) */ \ 85 (bt)->bt_addr = 0 << (shift); \ 86 (bt)->bt_cmap = (x); \ 87 if ((shift)) { \ 88 (bt)->bt_cmap = (x) << 8; \ 89 (bt)->bt_cmap = (x) << 16; \ 90 /* restore read mask */ \ 91 BT_INIT((bt), (shift)); \ 92 } while(0) 93 #define BT_BLANK(bt, shift) do { \ 94 (bt)->bt_addr = 0x06 << (shift); /* command reg */ \ 95 (bt)->bt_ctrl = 0x70 << (shift); /* overlay plane */ \ 96 (bt)->bt_addr = 0x04 << (shift); /* read mask */ \ 97 (bt)->bt_ctrl = 0x00 << (shift); /* color planes */ \ 98 /* Set color 0 to black -- note that this overwrites R of color 1. */\ 99 (bt)->bt_addr = 0 << (shift); \ 100 (bt)->bt_cmap = 0 << (shift); \ 101 /* restore read mask */ \ 102 BT_INIT((bt), (shift)); \ 103 } while(0) 104 105 106 /* 107 * Sbus framebuffer control look like this (usually at offset 0x400000). 108 */ 109 struct fbcontrol { 110 struct bt_regs fbc_dac; 111 u_char fbc_ctrl; 112 u_char fbc_status; 113 u_char fbc_cursor_start; 114 u_char fbc_cursor_end; 115 u_char fbc_vcontrol[12]; /* 12 bytes of video timing goo */ 116 }; 117 /* fbc_ctrl bits: */ 118 #define FBC_IENAB 0x80 /* Interrupt enable */ 119 #define FBC_VENAB 0x40 /* Video enable */ 120 #define FBC_TIMING 0x20 /* Master timing enable */ 121 #define FBC_CURSOR 0x10 /* Cursor compare enable */ 122 #define FBC_XTALMSK 0x0c /* Xtal select (0,1,2,test) */ 123 #define FBC_DIVMSK 0x03 /* Divisor (1,2,3,4) */ 124 125 /* fbc_status bits: */ 126 #define FBS_INTR 0x80 /* Interrupt pending */ 127 #define FBS_MSENSE 0x70 /* Monitor sense mask */ 128 #define FBS_1024X768 0x10 129 #define FBS_1152X900 0x30 130 #define FBS_1280X1024 0x40 131 #define FBS_1600X1280 0x50 132 #define FBS_ID_MASK 0x0f /* ID mask */ 133 #define FBS_ID_COLOR 0x01 134 #define FBS_ID_MONO 0x02 135 #define FBS_ID_MONO_ECL 0x03 /* ? */ 136 137
Indexes created Sun Sep 21 14:09:52 GMT 2025