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    Searched defs:fclk (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/arch/arm/ep93xx/
epsoc.c 79 uint64_t fclk, pclk, hclk; local
136 fclk = 14745600ULL * ((pll1x1fbd1 + 1) * (pll1x2fbd2 + 1)) /
138 hclk = fclk / hclkdivisors[hclkdiv];
142 fclk = fclk >> fclkdiv;
144 fclk = 14745600ULL;
146 printf("%s: fclk %lld.%02lld MHz hclk %lld.%02lld MHz pclk %lld.%02lld MHz\n",
148 fclk / 1000000, (fclk % 1000000 + 5000) / 10000,
152 sc->sc_fclk = fclk;
    [all...]
  /src/sys/dev/fdt/
fixedclock.c 153 struct fixedclock_clk *fclk = (struct fixedclock_clk *)clk; local
155 return fclk->rate;
fixedfactorclock.c 163 struct fixedfactorclock_clk *fclk = (struct fixedfactorclock_clk *)clk; local
170 return (clk_get_rate(clkp_parent) * fclk->mult) / fclk->div;
  /src/sys/arch/arm/arm32/
cpu.c 215 char *fclk; local
221 fclk = "bus clock";
224 fclk = "ref clock";
227 fclk = "pll";
230 fclk = "illegal";
233 aprint_normal(" fclk source=%s\n", fclk);
  /src/sys/arch/evbarm/stand/boot2440/
main.c 80 static void s3c24x0_clock_freq2(vaddr_t clkman_base, int *fclk, int *hclk,
112 int fclk, hclk; local
133 Target FCLK is 405MHz, and we assume an input crystal of 12MHz
146 s3c24x0_clock_freq2(S3C2440_CLKMAN_BASE, &fclk, &hclk, &pclk);
408 s3c24x0_clock_freq2(vaddr_t clkman_base, int *fclk, int *hclk, int *pclk)
429 /* 00b: HCLK = FCLK/1*/
432 /* 01b: HCLK = FCLK/2*/
436 /* 10b: HCLK = FCLK/4 when CAMDIVN[9] (HCLK4_HALF) = 0
437 * HCLK = FCLK/8 when CAMDIVN[9] (HCLK4_HALF) = 1 */
444 /* 11b: HCLK = FCLK/3 when CAMDIVN[8] (HCLK3_HALF) =
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
amdgpu_smu.h 229 uint32_t fclk; member in struct:smu_bios_boot_up_values

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