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      1 /*	$NetBSD: vectors.S,v 1.11 2022/10/20 06:58:38 skrll Exp $	*/
      2 
      3 /*
      4  * Copyright (C) 1994-1997 Mark Brinicombe
      5  * Copyright (C) 1994 Brini
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *	This product includes software developed by Brini.
     19  * 4. The name of Brini may not be used to endorse or promote products
     20  *    derived from this software without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
     23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     27  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     28  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     29  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     30  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
     31  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     32  */
     33 
     34 #include "assym.h"
     35 #include "opt_cputypes.h"
     36 #include "opt_cpuoptions.h"
     37 #include <machine/asm.h>
     38 
     39 /*
     40  * These are the exception vectors copied down to page 0.
     41  *
     42  * Note that FIQs are special; rather than using a level of
     43  * indirection, we actually copy the FIQ code down into the
     44  * vector page.
     45  */
     46 
     47 	.text
     48 	.global _C_LABEL(fiqvector)
     49 
     50 #if defined(CPU_ARMV7) || defined(CPU_ARM11) || defined(ARM_HAS_VBAR)
     51 	/*
     52 	 * ARMv[67] processors with the Security Extension have the VBAR
     53 	 * which redirects the low vector to any 32-byte aligned address.
     54 	 * Since we are in kernel, we can just do a relative branch to the
     55 	 * exception code and avoid the intermediate load.
     56 	 */
     57 	.global	_C_LABEL(page0rel)
     58 	.p2align 5
     59 _C_LABEL(page0rel):
     60 	b	reset_entry
     61 	b	undefined_entry
     62 	b	swi_entry
     63 	b	prefetch_abort_entry
     64 	b	data_abort_entry
     65 	b	address_exception_entry
     66 	b	irq_entry
     67 #ifdef __ARM_FIQ_INDIRECT
     68 	b	_C_LABEL(fiqvector)
     69 #else
     70 _C_LABEL(fiqbranch):
     71 	subs	pc, lr, #4
     72 #endif
     73 END(page0rel)
     74 
     75 #endif /* CPU_ARMV7 || CPU_ARM11 || ARM_HAS_VBAR */
     76 
     77 #if !defined(ARM_HAS_VBAR)
     78 
     79 	.global	_C_LABEL(page0), _C_LABEL(page0_data), _C_LABEL(page0_end)
     80 	.align	0
     81 _C_LABEL(page0):
     82 	ldr	pc, .Lreset_target
     83 	ldr	pc, .Lundefined_target
     84 	ldr	pc, .Lswi_target
     85 	ldr	pc, .Lprefetch_abort_target
     86 	ldr	pc, .Ldata_abort_target
     87 	ldr	pc, .Laddress_exception_target
     88 	ldr	pc, .Lirq_target
     89 #ifdef __ARM_FIQ_INDIRECT
     90 	ldr	pc, .Lfiq_target
     91 #else
     92 .Lfiqvector:
     93 	.set	_C_LABEL(fiqvector), . - _C_LABEL(page0)
     94 	subs	pc, lr, #4
     95 	.org	.Lfiqvector + 0x100
     96 END(page0)
     97 #endif
     98 
     99 _C_LABEL(page0_data):
    100 .Lreset_target:
    101 	.word	reset_entry
    102 
    103 .Lundefined_target:
    104 	.word	undefined_entry
    105 
    106 .Lswi_target:
    107 	.word	swi_entry
    108 
    109 .Lprefetch_abort_target:
    110 	.word	prefetch_abort_entry
    111 
    112 .Ldata_abort_target:
    113 	.word	data_abort_entry
    114 
    115 .Laddress_exception_target:
    116 	.word	address_exception_entry
    117 
    118 .Lirq_target:
    119 	.word	irq_entry
    120 
    121 #ifdef __ARM_FIQ_INDIRECT
    122 .Lfiq_target:
    123 	.word	_C_LABEL(fiqvector)
    124 #else
    125 	.word	0	/* pad it out */
    126 #endif
    127 _C_LABEL(page0_end):
    128 #endif /* ARM_HAS_VBAR */
    129 
    130 #ifdef __ARM_FIQ_INDIRECT
    131 	.data
    132 	.align	0
    133 _C_LABEL(fiqvector):
    134 	subs	pc, lr, #4
    135 	.org	_C_LABEL(fiqvector) + 0x100
    136 #endif
    137