1 /* $NetBSD: tegra_xusb.c,v 1.28 2021/08/07 16:18:44 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.28 2021/08/07 16:18:44 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 #include <arm/nvidia/tegra_xusbpad.h> 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <arm/nvidia/tegra_pmcreg.h> 47 48 #include <dev/pci/pcireg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #include <dev/firmload.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdivar.h> 57 #include <dev/usb/usb_mem.h> 58 59 #include <dev/usb/xhcireg.h> 60 #include <dev/usb/xhcivar.h> 61 62 #ifdef TEGRA_XUSB_DEBUG 63 int tegra_xusb_debug = 1; 64 #else 65 int tegra_xusb_debug = 0; 66 #endif 67 68 #define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__) 69 70 static int tegra_xusb_match(device_t, cfdata_t, void *); 71 static void tegra_xusb_attach(device_t, device_t, void *); 72 static void tegra_xusb_mountroot(device_t); 73 74 static int tegra_xusb_intr_mbox(void *); 75 76 #ifdef TEGRA124_XUSB_BIN_STATIC 77 extern const char _binary_tegra124_xusb_bin_start[]; 78 extern const char _binary_tegra124_xusb_bin_end[]; 79 __asm__( 80 ".section \".rodata\"\n" 81 "_binary_tegra124_xusb_bin_start:\n" 82 ".incbin \"../external/nvidia-firmware/tegra/dist/tegra124/xusb.bin\"\n" 83 ".size _binary_tegra124_xusb_bin_start, . - _binary_tegra124_xusb_bin_start\n" 84 "_binary_tegra124_xusb_bin_end:\n" 85 ".previous\n" 86 ); 87 #endif 88 89 #ifdef TEGRA210_XUSB_BIN_STATIC 90 extern const char _binary_tegra210_xusb_bin_start[]; 91 extern const char _binary_tegra210_xusb_bin_end[]; 92 __asm__( 93 ".section \".rodata\"\n" 94 "_binary_tegra210_xusb_bin_start:\n" 95 ".incbin \"../external/nvidia-firmware/tegra/dist/tegra210/xusb.bin\"\n" 96 ".size _binary_tegra210_xusb_bin_start, . - _binary_tegra210_xusb_bin_start\n" 97 "_binary_tegra210_xusb_bin_end:\n" 98 ".previous\n" 99 ); 100 #endif 101 102 enum xusb_type { 103 XUSB_T124 = 1, 104 XUSB_T210 105 }; 106 107 struct tegra_xhci_data { 108 enum xusb_type txd_type; 109 const char * const * txd_supplies; 110 size_t txd_nsupplies; 111 bool txd_scale_ss_clock; 112 }; 113 114 const char *tegra124_xhci_supplies[] = { 115 "dvddio-pex-supply", 116 "hvddio-pex-supply", 117 "avdd-usb-supply", 118 "avdd-pll-utmip-supply", 119 "avdd-pll-uerefe-supply", 120 "dvdd-usb-ss-pll-supply", 121 "hvdd-usb-ss-pll-e-supply" 122 }; 123 124 struct tegra_xhci_data tegra124_xhci_data = { 125 .txd_type = XUSB_T124, 126 .txd_supplies = tegra124_xhci_supplies, 127 .txd_nsupplies = __arraycount(tegra124_xhci_supplies), 128 .txd_scale_ss_clock = true, 129 }; 130 131 const char *tegra210_xhci_supplies[] = { 132 "dvddio-pex", 133 "hvddio-pex", 134 "avdd-usb", 135 "avdd-pll-utmip", 136 "avdd-pll-uerefe", 137 "dvdd-pex-pll", 138 "hvdd-pex-pll-e", 139 }; 140 141 struct tegra_xhci_data tegra210_xhci_data = { 142 .txd_type = XUSB_T210, 143 .txd_supplies = tegra210_xhci_supplies, 144 .txd_nsupplies = __arraycount(tegra210_xhci_supplies), 145 .txd_scale_ss_clock = false, 146 }; 147 148 static const struct device_compatible_entry compat_data[] = { 149 { .compat = "nvidia,tegra124-xusb", .data = &tegra124_xhci_data }, 150 { .compat = "nvidia,tegra210-xusb", .data = &tegra210_xhci_data }, 151 DEVICE_COMPAT_EOL 152 }; 153 154 struct fw_dma { 155 bus_dmamap_t map; 156 void * addr; 157 bus_dma_segment_t segs[1]; 158 int nsegs; 159 size_t size; 160 }; 161 162 struct tegra_xusb_softc { 163 struct xhci_softc sc_xhci; 164 int sc_phandle; 165 bus_space_handle_t sc_bsh_xhci; 166 bus_space_handle_t sc_bsh_fpci; 167 bus_space_handle_t sc_bsh_ipfs; 168 void *sc_ih; 169 void *sc_ih_mbox; 170 struct fw_dma sc_fw_dma; 171 struct clk *sc_clk_ss_src; 172 173 const struct tegra_xhci_data *sc_txd; 174 }; 175 176 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 177 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 178 uint32_t); 179 180 static void tegra_xusb_init(struct tegra_xusb_softc * const); 181 static int tegra_xusb_open_fw(struct tegra_xusb_softc * const); 182 static int tegra_xusb_load_fw(struct tegra_xusb_softc * const, void *, 183 size_t); 184 static void tegra_xusb_init_regulators(struct tegra_xusb_softc * const); 185 186 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 187 188 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 189 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 190 191 static int 192 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 193 { 194 struct fdt_attach_args * const faa = aux; 195 196 return of_compatible_match(faa->faa_phandle, compat_data); 197 } 198 199 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 200 do { \ 201 if (cond) { \ 202 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 203 return; \ 204 } \ 205 } while (0) 206 207 static void 208 tegra_xusb_attach(device_t parent, device_t self, void *aux) 209 { 210 struct tegra_xusb_softc * const psc = device_private(self); 211 struct xhci_softc * const sc = &psc->sc_xhci; 212 struct fdt_attach_args * const faa = aux; 213 bool wait_for_root = true; 214 char intrstr[128]; 215 bus_addr_t addr; 216 bus_size_t size; 217 struct fdtbus_reset *rst; 218 struct fdtbus_phy *phy; 219 struct clk *clk; 220 uint32_t rate; 221 int error, n; 222 223 aprint_naive("\n"); 224 aprint_normal(": XUSB\n"); 225 226 sc->sc_dev = self; 227 sc->sc_iot = faa->faa_bst; 228 sc->sc_bus.ub_hcpriv = sc; 229 sc->sc_bus.ub_dmatag = faa->faa_dmat; 230 sc->sc_quirks = XHCI_DEFERRED_START; 231 psc->sc_phandle = faa->faa_phandle; 232 233 psc->sc_txd = of_compatible_lookup(faa->faa_phandle, compat_data)->data; 234 235 if (fdtbus_get_reg_byname(faa->faa_phandle, "hcd", &addr, &size) != 0) { 236 aprint_error(": couldn't get registers\n"); 237 return; 238 } 239 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 240 if (error) { 241 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 242 return; 243 } 244 DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr); 245 sc->sc_ios = size; 246 247 if (fdtbus_get_reg_byname(faa->faa_phandle, "fpci", &addr, &size) != 0) { 248 aprint_error(": couldn't get registers\n"); 249 return; 250 } 251 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 252 if (error) { 253 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 254 return; 255 } 256 DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr); 257 258 if (fdtbus_get_reg_byname(faa->faa_phandle, "ipfs", &addr, &size) != 0) { 259 aprint_error(": couldn't get registers\n"); 260 return; 261 } 262 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 263 if (error) { 264 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 265 return; 266 } 267 DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr); 268 269 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 270 aprint_error_dev(self, "failed to decode interrupt\n"); 271 return; 272 } 273 274 psc->sc_ih = fdtbus_intr_establish_xname(faa->faa_phandle, 0, IPL_USB, 275 FDT_INTR_MPSAFE, xhci_intr, sc, device_xname(self)); 276 if (psc->sc_ih == NULL) { 277 aprint_error_dev(self, "failed to establish interrupt on %s\n", 278 intrstr); 279 return; 280 } 281 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 282 283 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 284 aprint_error_dev(self, "failed to decode interrupt\n"); 285 return; 286 } 287 288 psc->sc_ih_mbox = fdtbus_intr_establish_xname(faa->faa_phandle, 1, 289 IPL_VM, FDT_INTR_MPSAFE, tegra_xusb_intr_mbox, psc, 290 device_xname(self)); 291 if (psc->sc_ih_mbox == NULL) { 292 aprint_error_dev(self, "failed to establish interrupt on %s\n", 293 intrstr); 294 return; 295 } 296 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 297 298 /* Enable PHYs */ 299 for (n = 0; (phy = fdtbus_phy_get_index(faa->faa_phandle, n)) != NULL; n++) 300 if (fdtbus_phy_enable(phy, true) != 0) 301 aprint_error_dev(self, "failed to enable PHY #%d\n", n); 302 303 /* Enable XUSB power rails */ 304 305 tegra_pmc_power(PMC_PARTID_XUSBC, true); /* Host/USB2.0 */ 306 tegra_pmc_remove_clamping(PMC_PARTID_XUSBC); 307 tegra_pmc_power(PMC_PARTID_XUSBA, true); /* SuperSpeed */ 308 tegra_pmc_remove_clamping(PMC_PARTID_XUSBA); 309 310 /* Enable XUSB clocks */ 311 312 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 313 rate = clk_get_rate(clk); 314 error = clk_enable(clk); /* XXX set frequency */ 315 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 316 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 317 318 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 319 rate = clk_get_rate(clk); 320 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 321 error = clk_set_rate(clk, 102000000); 322 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 323 324 rate = clk_get_rate(clk); 325 error = clk_enable(clk); /* XXX set frequency */ 326 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 327 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 328 329 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 330 rate = clk_get_rate(clk); 331 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 332 error = clk_set_rate(clk, 204000000); 333 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 334 335 rate = clk_get_rate(clk); 336 error = clk_enable(clk); 337 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 338 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 339 340 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 341 rate = clk_get_rate(clk); 342 error = clk_enable(clk); /* XXX set frequency */ 343 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 344 345 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 346 rate = clk_get_rate(clk); 347 error = clk_enable(clk); /* XXX set frequency */ 348 DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 349 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 350 351 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 352 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 353 "failed to get xusb_ss_src clock"); 354 355 if (psc->sc_txd->txd_scale_ss_clock) { 356 rate = clk_get_rate(psc->sc_clk_ss_src); 357 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 358 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 359 rate = clk_get_rate(psc->sc_clk_ss_src); 360 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error); 361 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 362 363 rate = clk_get_rate(psc->sc_clk_ss_src); 364 DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate); 365 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 366 367 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 368 rate = clk_get_rate(psc->sc_clk_ss_src); 369 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 370 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 371 } 372 373 rate = clk_get_rate(psc->sc_clk_ss_src); 374 error = clk_enable(psc->sc_clk_ss_src); 375 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 376 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 377 378 #if 0 379 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 380 error = 0; 381 rate = clk_get_rate(clk); 382 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 383 #endif 384 385 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 386 rate = clk_get_rate(clk); 387 error = clk_enable(clk); /* XXX set frequency */ 388 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 389 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 390 391 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 392 fdtbus_reset_deassert(rst); 393 394 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 395 fdtbus_reset_deassert(rst); 396 397 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 398 fdtbus_reset_deassert(rst); 399 400 DELAY(1); 401 402 tegra_xusb_init_regulators(psc); 403 404 tegra_xusb_init(psc); 405 406 #if defined(TEGRA124_XUSB_BIN_STATIC) 407 if (psc->sc_txd->txd_type == XUSB_T124) 408 wait_for_root = false; 409 #endif 410 #if defined(TEGRA210_XUSB_BIN_STATIC) 411 if (psc->sc_txd->txd_type == XUSB_T210) 412 wait_for_root = false; 413 #endif 414 415 if (wait_for_root) 416 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 417 else 418 tegra_xusb_mountroot(sc->sc_dev); 419 } 420 421 static void 422 tegra_xusb_mountroot(device_t self) 423 { 424 struct tegra_xusb_softc * const psc = device_private(self); 425 struct xhci_softc * const sc = &psc->sc_xhci; 426 const bus_space_tag_t bst = sc->sc_iot; 427 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 428 struct clk *clk; 429 struct fdtbus_reset *rst; 430 uint32_t rate; 431 uint32_t val; 432 int error; 433 434 DPRINTF(sc->sc_dev, "%s()\n", __func__); 435 436 val = bus_space_read_4(bst, ipfsh, 0x0); 437 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 438 439 if (tegra_xusb_open_fw(psc) != 0) 440 return; 441 DPRINTF(sc->sc_dev, "post fw\n"); 442 443 tegra_xusbpad_xhci_enable(); 444 445 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 446 rate = clk_get_rate(clk); 447 error = clk_enable(clk); 448 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 449 450 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 451 rate = clk_get_rate(clk); 452 error = clk_enable(clk); 453 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 454 455 val = bus_space_read_4(bst, ipfsh, 0x0); 456 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 457 458 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 459 fdtbus_reset_deassert(rst); 460 461 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 462 fdtbus_reset_deassert(rst); 463 464 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 465 fdtbus_reset_deassert(rst); 466 467 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 468 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 469 470 val = bus_space_read_4(bst, psc->sc_bsh_fpci, PCI_USBREV) 471 & PCI_USBREV_MASK; 472 switch (val) { 473 case PCI_USBREV_3_0: 474 sc->sc_bus.ub_revision = USBREV_3_0; 475 break; 476 case PCI_USBREV_3_1: 477 sc->sc_bus.ub_revision = USBREV_3_1; 478 break; 479 default: 480 if (val < PCI_USBREV_3_0) { 481 aprint_error_dev(self, "Unknown revision (%02x)\n", val); 482 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 483 } else { 484 /* Default to the latest revision */ 485 aprint_normal_dev(self, 486 "Unknown revision (%02x). Set to 3.1.\n", val); 487 sc->sc_bus.ub_revision = USBREV_3_1; 488 } 489 break; 490 } 491 492 error = xhci_init(sc); 493 if (error) { 494 aprint_error_dev(self, "init failed, error=%d\n", error); 495 return; 496 } 497 498 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint, CFARGS_NONE); 499 500 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint, 501 CFARGS_NONE); 502 503 xhci_start(sc); 504 505 error = xusb_mailbox_send(psc, 0x01000000); 506 if (error) { 507 aprint_error_dev(self, "send failed, error=%d\n", error); 508 } 509 } 510 511 static int 512 tegra_xusb_intr_mbox(void *v) 513 { 514 struct tegra_xusb_softc * const psc = v; 515 struct xhci_softc * const sc = &psc->sc_xhci; 516 const bus_space_tag_t bst = sc->sc_iot; 517 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 518 uint32_t val; 519 uint32_t irv; 520 uint32_t msg; 521 int error; 522 523 DPRINTF(sc->sc_dev, "%s()\n", __func__); 524 525 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 526 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 527 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 528 529 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 530 aprint_error_dev(sc->sc_dev, "firmware hang\n"); 531 532 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 533 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 534 535 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 536 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 537 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 538 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 539 540 bool sendresp = true; 541 u_int rate; 542 543 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 544 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 545 546 switch (type) { 547 case 2: 548 case 3: 549 DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 550 break; 551 case 4: 552 case 5: 553 if (psc->sc_txd->txd_scale_ss_clock) { 554 DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 555 rate = clk_get_rate(psc->sc_clk_ss_src); 556 DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 557 rate); 558 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 559 if (error != 0) 560 goto clk_fail; 561 rate = clk_get_rate(psc->sc_clk_ss_src); 562 DPRINTF(sc->sc_dev, 563 "rate of psc->sc_clk_ss_src %u after\n", rate); 564 if (data == (rate / 1000)) { 565 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 566 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 567 } else 568 clk_fail: 569 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 570 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 571 } else { 572 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 573 __SHIFTIN(data, MAILBOX_DATA_DATA); 574 } 575 xusb_mailbox_send(psc, msg); 576 break; 577 case 9: 578 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 579 __SHIFTIN(128, MAILBOX_DATA_TYPE); 580 xusb_mailbox_send(psc, msg); 581 break; 582 case 6: 583 case 128: 584 case 129: 585 sendresp = false; 586 break; 587 default: 588 sendresp = false; 589 break; 590 } 591 592 if (sendresp == false) 593 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 594 MAILBOX_OWNER_NONE); 595 596 return irv; 597 } 598 599 static void 600 tegra_xusb_init_regulators(struct tegra_xusb_softc * const psc) 601 { 602 603 device_t dev = psc->sc_xhci.sc_dev; 604 const int phandle = psc->sc_phandle; 605 struct fdtbus_regulator *reg; 606 int n, error; 607 608 for (n = 0; n < psc->sc_txd->txd_nsupplies; n++) { 609 if (!of_hasprop(phandle, psc->sc_txd->txd_supplies[n])) 610 continue; 611 reg = fdtbus_regulator_acquire(phandle, psc->sc_txd->txd_supplies[n]); 612 if (reg == NULL) { 613 aprint_error_dev(dev, "couldn't acquire supply '%s'\n", 614 psc->sc_txd->txd_supplies[n]); 615 continue; 616 } 617 error = fdtbus_regulator_enable(reg); 618 if (error != 0) 619 aprint_error_dev(dev, "couldn't enable supply '%s': %d\n", 620 psc->sc_txd->txd_supplies[n], error); 621 } 622 } 623 624 static void 625 tegra_xusb_init(struct tegra_xusb_softc * const psc) 626 { 627 struct xhci_softc * const sc = &psc->sc_xhci; 628 const bus_space_tag_t bst = sc->sc_iot; 629 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 630 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 631 632 DPRINTF(sc->sc_dev, "%s()\n", __func__); 633 634 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 635 bus_space_read_4(bst, ipfsh, 0x0)); 636 637 DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 638 bus_space_read_4(bst, ipfsh, 0x40)); 639 640 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 641 bus_space_read_4(bst, ipfsh, 0x80)); 642 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 643 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 644 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 645 bus_space_read_4(bst, ipfsh, 0x80)); 646 647 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 648 bus_space_read_4(bst, ipfsh, 0x180)); 649 /* EN_FPCI */ 650 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 651 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 652 bus_space_read_4(bst, ipfsh, 0x180)); 653 654 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 655 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 656 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 657 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 658 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 659 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 660 661 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 662 bus_space_read_4(bst, fpcih, PCI_BAR0)); 663 /* match FPCI BAR0 to above */ 664 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 665 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 666 bus_space_read_4(bst, fpcih, PCI_BAR0)); 667 668 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 669 bus_space_read_4(bst, ipfsh, 0x188)); 670 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 671 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 672 bus_space_read_4(bst, ipfsh, 0x188)); 673 674 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 675 bus_space_read_4(bst, fpcih, 0x1bc)); 676 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 677 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 678 bus_space_read_4(bst, fpcih, 0x1bc)); 679 } 680 681 static int 682 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 683 struct fw_dma * const p) 684 { 685 struct xhci_softc * const sc = &psc->sc_xhci; 686 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 687 int err; 688 689 p->size = size; 690 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 691 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 692 if (err) 693 return err; 694 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 695 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 696 if (err) 697 goto free; 698 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 699 &p->map); 700 if (err) 701 goto unmap; 702 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 703 BUS_DMA_NOWAIT); 704 if (err) 705 goto destroy; 706 707 return 0; 708 709 destroy: 710 bus_dmamap_destroy(dmat, p->map); 711 unmap: 712 bus_dmamem_unmap(dmat, p->addr, p->size); 713 free: 714 bus_dmamem_free(dmat, p->segs, p->nsegs); 715 716 return err; 717 } 718 719 static void 720 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 721 { 722 const struct xhci_softc * const sc = &psc->sc_xhci; 723 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 724 725 bus_dmamap_unload(dmat, p->map); 726 bus_dmamap_destroy(dmat, p->map); 727 bus_dmamem_unmap(dmat, p->addr, p->size); 728 bus_dmamem_free(dmat, p->segs, p->nsegs); 729 } 730 731 #define FWHEADER_BOOT_CODETAG 8 732 #define FWHEADER_BOOT_CODESIZE 12 733 #define FWHEADER_FWIMG_LEN 100 734 #define FWHEADER__LEN 256 735 736 static int 737 tegra_xusb_open_fw(struct tegra_xusb_softc * const psc) 738 { 739 struct xhci_softc * const sc = &psc->sc_xhci; 740 firmware_handle_t fw; 741 size_t firmware_size = 0; 742 void *firmware_image; 743 const char *fw_path = NULL; 744 void *fw_static = NULL; 745 int error; 746 747 switch (psc->sc_txd->txd_type) { 748 case XUSB_T124: 749 #if defined(TEGRA124_XUSB_BIN_STATIC) 750 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_end 751 - (uintptr_t)&_binary_tegra124_xusb_bin_start; 752 fw_static = __UNCONST(_binary_tegra124_xusb_bin_start); 753 #else 754 fw_path = "nvidia/tegra124"; 755 #endif 756 break; 757 case XUSB_T210: 758 #if defined(TEGRA210_XUSB_BIN_STATIC) 759 firmware_size = (uintptr_t)&_binary_tegra210_xusb_bin_end 760 - (uintptr_t)&_binary_tegra210_xusb_bin_start; 761 fw_static = __UNCONST(_binary_tegra210_xusb_bin_start); 762 #else 763 fw_path = "nvidia/tegra210"; 764 #endif 765 break; 766 default: 767 return EINVAL; 768 } 769 770 if (fw_path != NULL) { 771 error = firmware_open(fw_path, "xusb.bin", &fw); 772 if (error != 0) { 773 aprint_error_dev(sc->sc_dev, 774 "couldn't load firmware from %s/xusb.bin: %d\n", 775 fw_path, error); 776 return error; 777 } 778 firmware_size = firmware_get_size(fw); 779 } 780 781 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, 782 &psc->sc_fw_dma); 783 if (error != 0) 784 return error; 785 firmware_image = psc->sc_fw_dma.addr; 786 787 if (fw_path != NULL) { 788 error = firmware_read(fw, 0, firmware_image, firmware_size); 789 if (error != 0) { 790 fw_dma_free(psc, &psc->sc_fw_dma); 791 firmware_close(fw); 792 return error; 793 } 794 firmware_close(fw); 795 } else { 796 memcpy(firmware_image, fw_static, firmware_size); 797 } 798 799 return tegra_xusb_load_fw(psc, firmware_image, firmware_size); 800 } 801 802 static int 803 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc, void *firmware_image, 804 size_t firmware_size) 805 { 806 struct xhci_softc * const sc = &psc->sc_xhci; 807 const uint8_t *header; 808 809 header = firmware_image; 810 811 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 812 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 813 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 814 815 if (fwimg_len != firmware_size) 816 aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 817 fwimg_len, firmware_size); 818 819 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 820 firmware_size, BUS_DMASYNC_PREWRITE); 821 822 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 823 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 824 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 825 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 826 827 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 828 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 829 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 830 fwimg_len); 831 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 832 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 833 834 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 835 FWHEADER__LEN; 836 837 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 838 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 839 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 840 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 841 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 842 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 843 844 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 845 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 846 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 847 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 848 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 849 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 850 851 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 852 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 853 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 854 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 855 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 856 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 857 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 858 859 const u_int code_tag_blocks = 860 howmany(boot_codetag, IMEM_BLOCK_SIZE); 861 const u_int code_size_blocks = 862 howmany(boot_codesize, IMEM_BLOCK_SIZE); 863 const u_int code_blocks = code_tag_blocks + code_size_blocks; 864 865 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 866 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 867 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 868 __SHIFTIN(code_tag_blocks, 869 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 870 __SHIFTIN(code_size_blocks, 871 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 872 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 873 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 874 875 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 876 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 877 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 878 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 879 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 880 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 881 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 882 883 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 884 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 885 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 886 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 887 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 888 889 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 890 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 891 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 892 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 893 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 894 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 895 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 896 897 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 898 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 899 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 900 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 901 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 902 903 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 904 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 905 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 906 boot_codetag); 907 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 908 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 909 910 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 911 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 912 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 913 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 914 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 915 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 916 917 return 0; 918 } 919 920 static uint32_t 921 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 922 { 923 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 924 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 925 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 926 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 927 928 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 929 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 930 } 931 932 static void 933 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 934 uint32_t value) 935 { 936 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 937 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 938 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 939 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 940 941 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 942 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 943 } 944 945 static int 946 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 947 { 948 struct xhci_softc * const sc = &psc->sc_xhci; 949 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 950 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 951 uint32_t val; 952 bool wait = false; 953 954 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 955 956 if (!(type == 128 || type == 129)) { 957 val = bus_space_read_4(bst, fpcih, 958 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 959 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 960 val); 961 if (val != MAILBOX_OWNER_NONE) { 962 return EBUSY; 963 } 964 965 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 966 MAILBOX_OWNER_SW); 967 968 val = bus_space_read_4(bst, fpcih, 969 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 970 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 971 val); 972 if (val != MAILBOX_OWNER_SW) { 973 return EBUSY; 974 } 975 976 wait = true; 977 } 978 979 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 980 981 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 982 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 983 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 984 985 if (wait) { 986 987 for (u_int i = 0; i < 2500; i++) { 988 val = bus_space_read_4(bst, fpcih, 989 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 990 DPRINTF(sc->sc_dev, 991 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 992 if (val == MAILBOX_OWNER_NONE) { 993 break; 994 } 995 DELAY(10); 996 } 997 998 val = bus_space_read_4(bst, fpcih, 999 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 1000 DPRINTF(sc->sc_dev, 1001 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 1002 if (val != MAILBOX_OWNER_NONE) { 1003 aprint_error_dev(sc->sc_dev, 1004 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 1005 } 1006 } 1007 1008 return 0; 1009 } 1010
Indexes created Tue Sep 23 13:09:54 GMT 2025