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    Searched defs:gpu_addr (Results 1 - 25 of 27) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cgs.c 216 uint64_t gpu_addr; local in function:amdgpu_cgs_get_firmware_info
227 gpu_addr = ucode->mc_addr;
233 gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE);
239 info->mc_addr = gpu_addr;
amdgpu_ih.h 51 uint64_t gpu_addr; member in struct:amdgpu_ih_ring
amdgpu_vce.h 39 uint64_t gpu_addr; member in struct:amdgpu_vce
amdgpu_uvd.h 45 uint64_t gpu_addr; member in struct:amdgpu_uvd_inst
amdgpu_si_dma.c 80 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
81 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
161 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
168 WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
214 u64 gpu_addr; local in function:si_dma_ring_test_ring
220 gpu_addr = adev->wb.gpu_addr + (index * 4);
229 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
230 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
264 u64 gpu_addr; local in function:si_dma_ring_test_ib
    [all...]
amdgpu_cik_sdma.c 239 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
240 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
483 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
485 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
489 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
490 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
625 u64 gpu_addr; local in function:cik_sdma_ring_test_ring
631 gpu_addr = adev->wb.gpu_addr + (index * 4);
640 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
676 u64 gpu_addr; local in function:cik_sdma_ring_test_ib
    [all...]
amdgpu_sdma_v2_4.c 269 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
270 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
462 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
464 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
468 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
469 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
560 u64 gpu_addr; local in function:sdma_v2_4_ring_test_ring
566 gpu_addr = adev->wb.gpu_addr + (index * 4);
576 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
612 u64 gpu_addr; local in function:sdma_v2_4_ring_test_ib
    [all...]
amdgpu_vcn.h 177 uint64_t gpu_addr; member in struct:amdgpu_vcn_inst
amdgpu_virt.h 38 uint64_t gpu_addr; member in struct:amdgpu_mm_table
amdgpu_ring.h 76 uint64_t gpu_addr; member in struct:amdgpu_fence_driver
196 uint64_t gpu_addr; member in struct:amdgpu_ring
amdgpu_sdma_v3_0.c 443 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
444 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
701 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
703 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
707 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
708 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
722 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
832 u64 gpu_addr; local in function:sdma_v3_0_ring_test_ring
838 gpu_addr = adev->wb.gpu_addr + (index * 4)
884 u64 gpu_addr; local in function:sdma_v3_0_ring_test_ib
    [all...]
amdgpu_sdma_v4_0.c 813 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
814 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1113 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1115 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1120 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1121 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1145 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1203 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1205 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1210 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8)
1486 u64 gpu_addr; local in function:sdma_v4_0_ring_test_ring
1539 u64 gpu_addr; local in function:sdma_v4_0_ring_test_ib
    [all...]
amdgpu_sdma_v5_0.c 405 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
406 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
653 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
668 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
670 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
674 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
675 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
887 u64 gpu_addr; local in function:sdma_v5_0_ring_test_ring
895 gpu_addr = adev->wb.gpu_addr + (index * 4)
948 u64 gpu_addr; local in function:sdma_v5_0_ring_test_ib
    [all...]
amdgpu_gfx_v10_0.c 286 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
311 u64 gpu_addr, u64 seq)
325 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
326 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
2172 uint64_t gpu_addr; local in function:gfx_v10_0_rlc_backdoor_autoload_enable
2180 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
2182 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
2183 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
2804 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2809 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4)
    [all...]
amdgpu_gfx_v8_0.c 888 uint64_t gpu_addr; local in function:gfx_v8_0_ring_test_ib
896 gpu_addr = adev->wb.gpu_addr + (index * 4);
905 ib.ptr[2] = lower_32_bits(gpu_addr);
906 ib.ptr[3] = upper_32_bits(gpu_addr);
1530 u64 gpu_addr; local in function:gfx_v8_0_do_edc_gpr_workarounds
1581 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1584 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1585 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
    [all...]
amdgpu_gfx_v9_0.c 775 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
804 u64 gpu_addr, u64 seq)
818 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
819 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
1023 uint64_t gpu_addr; local in function:gfx_v9_0_ring_test_ib
1031 gpu_addr = adev->wb.gpu_addr + (index * 4);
1040 ib.ptr[2] = lower_32_bits(gpu_addr);
1041 ib.ptr[3] = upper_32_bits(gpu_addr);
3205 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4)
4207 u64 gpu_addr; local in function:gfx_v9_0_do_edc_gpr_workarounds
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_gart.c 213 uint64_t gpu_addr; local in function:radeon_gart_table_vram_pin
220 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
229 rdev->gart.table_addr = gpu_addr;
radeon_r600_dma.c 149 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
151 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
156 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
241 u64 gpu_addr; local in function:r600_dma_ring_test
248 gpu_addr = rdev->wb.gpu_addr + index;
259 radeon_ring_write(ring, lower_32_bits(gpu_addr));
260 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
295 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
322 u64 addr = semaphore->gpu_addr;
348 u64 gpu_addr; local in function:r600_dma_ib_test
    [all...]
radeon_cik_sdma.c 160 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
161 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
209 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
238 u64 addr = semaphore->gpu_addr;
406 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
408 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
413 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
414 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
657 u64 gpu_addr; local in function:cik_sdma_ring_test
664 gpu_addr = rdev->wb.gpu_addr + index
714 u64 gpu_addr; local in function:cik_sdma_ib_test
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/inc/
dmub_srv.h 135 * @gpu_addr: gpu virtual address for the region, NULL if invalid
140 uint64_t gpu_addr; member in struct:dmub_fb
183 * @gpu_addr: base gpu virtual address for the framebuffer
188 uint64_t gpu_addr; member in struct:dmub_srv_fb_params
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm.h 86 * @gpu_addr: MMIO gpu addr
91 uint64_t gpu_addr; member in struct:dm_comressor_info
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_amd_powerplay.c 152 uint64_t gpu_addr; local in function:pp_reserve_vram_for_smu
158 &gpu_addr,
168 lower_32_bits(gpu_addr),
169 upper_32_bits(gpu_addr),
  /src/sys/external/bsd/drm/dist/shared-core/
r600_blit.c 1202 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr)
1222 OUT_RING(gpu_addr >> 8);
1229 OUT_RING(gpu_addr >> 8);
1285 u64 gpu_addr; local in function:set_shaders
1305 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset;
1314 OUT_RING(gpu_addr >> 8);
1327 OUT_RING((gpu_addr + 256) >> 8);
1343 R600_SH_ACTION_ENA, 512, gpu_addr);
1347 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
1353 sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8))
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/ast/
ast_mode.c 574 s64 gpu_addr; local in function:ast_primary_plane_helper_atomic_update
577 gpu_addr = drm_gem_vram_offset(gbo);
578 if (WARN_ON_ONCE(gpu_addr < 0))
582 ast_set_start_address_crt1(ast, (u32)gpu_addr);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/
kfd_priv.h 216 uint64_t gpu_addr; member in struct:kfd_mem_obj
961 int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer);

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