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      1 /*	$NetBSD: igc_base.h,v 1.2 2023/10/04 07:35:27 rin Exp $	*/
      2 /*	$OpenBSD: igc_base.h,v 1.1 2021/10/31 14:52:57 patrick Exp $	*/
      3 /*-
      4  * Copyright 2021 Intel Corp
      5  * Copyright 2021 Rubicon Communications, LLC (Netgate)
      6  * SPDX-License-Identifier: BSD-3-Clause
      7  *
      8  * $FreeBSD$
      9  */
     10 
     11 #ifndef _IGC_BASE_H_
     12 #define _IGC_BASE_H_
     13 
     14 /* Forward declaration */
     15 struct igc_hw;
     16 
     17 int		igc_init_hw_base(struct igc_hw *hw);
     18 void		igc_power_down_phy_copper_base(struct igc_hw *hw);
     19 extern void	igc_rx_fifo_flush_base(struct igc_hw *hw);
     20 int		igc_acquire_phy_base(struct igc_hw *hw);
     21 void		igc_release_phy_base(struct igc_hw *hw);
     22 
     23 /* Transmit Descriptor - Advanced */
     24 union igc_adv_tx_desc {
     25 	struct {
     26 		uint64_t buffer_addr;	/* Address of descriptor's data buf */
     27 		uint32_t cmd_type_len;
     28 		uint32_t olinfo_status;
     29 	} read;
     30 	struct {
     31 		uint64_t rsvd;		/* Reserved */
     32 		uint32_t nxtseq_seed;
     33 		uint32_t status;
     34 	} wb;
     35 };
     36 
     37 /* Context descriptors */
     38 struct igc_adv_tx_context_desc {
     39 	uint32_t vlan_macip_lens;
     40 	union {
     41 		uint32_t launch_time;
     42 		uint32_t seqnum_seed;
     43 	};
     44 	uint32_t type_tucmd_mlhl;
     45 	uint32_t mss_l4len_idx;
     46 };
     47 
     48 /* Adv Transmit Descriptor Config Masks */
     49 #define IGC_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
     50 #define IGC_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
     51 #define IGC_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
     52 #define IGC_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
     53 #define IGC_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
     54 #define IGC_ADVTXD_DCMD_DDTYP_ISCSI	0x10000000 /* DDP hdr type or iSCSI */
     55 #define IGC_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
     56 #define IGC_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
     57 #define IGC_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
     58 #define IGC_ADVTXD_MAC_LINKSEC	0x00040000 /* Apply LinkSec on pkt */
     59 #define IGC_ADVTXD_MAC_TSTAMP	0x00080000 /* IEEE1588 Timestamp pkt */
     60 #define IGC_ADVTXD_STAT_SN_CRC	0x00000002 /* NXTSEQ/SEED prsnt in WB */
     61 #define IGC_ADVTXD_IDX_SHIFT	4 /* Adv desc Index shift */
     62 #define IGC_ADVTXD_POPTS_ISCO_1ST	0x00000000 /* 1st TSO of iSCSI PDU */
     63 #define IGC_ADVTXD_POPTS_ISCO_MDL	0x00000800 /* Middle TSO of iSCSI PDU */
     64 #define IGC_ADVTXD_POPTS_ISCO_LAST	0x00001000 /* Last TSO of iSCSI PDU */
     65 /* 1st & Last TSO-full iSCSI PDU*/
     66 #define IGC_ADVTXD_POPTS_ISCO_FULL	0x00001800
     67 #define IGC_ADVTXD_POPTS_IPSEC	0x00000400 /* IPSec offload request */
     68 #define IGC_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
     69 
     70 /* Advanced Transmit Context Descriptor Config */
     71 #define IGC_ADVTXD_MACLEN_SHIFT		9 /* Adv ctxt desc mac len shift */
     72 #define IGC_ADVTXD_VLAN_SHIFT		16 /* Adv ctxt vlan tag shift */
     73 #define IGC_ADVTXD_TUCMD_IPV4		0x00000400 /* IP Packet Type: 1=IPv4 */
     74 #define IGC_ADVTXD_TUCMD_IPV6		0x00000000 /* IP Packet Type: 0=IPv6 */
     75 #define IGC_ADVTXD_TUCMD_L4T_UDP	0x00000000 /* L4 Packet TYPE of UDP */
     76 #define IGC_ADVTXD_TUCMD_L4T_TCP	0x00000800 /* L4 Packet TYPE of TCP */
     77 #define IGC_ADVTXD_TUCMD_L4T_SCTP	0x00001000 /* L4 Packet TYPE of SCTP */
     78 #define IGC_ADVTXD_TUCMD_IPSEC_TYPE_ESP	0x00002000 /* IPSec Type ESP */
     79 /* IPSec Encrypt Enable for ESP */
     80 #define IGC_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN	0x00004000
     81 /* Req requires Markers and CRC */
     82 #define IGC_ADVTXD_TUCMD_MKRREQ		0x00002000
     83 #define IGC_ADVTXD_L4LEN_SHIFT		8 	/* Adv ctxt L4LEN shift */
     84 #define IGC_ADVTXD_MSS_SHIFT		16	/* Adv ctxt MSS shift */
     85 /* Adv ctxt IPSec SA IDX mask */
     86 #define IGC_ADVTXD_IPSEC_SA_INDEX_MASK	0x000000FF
     87 /* Adv ctxt IPSec ESP len mask */
     88 #define IGC_ADVTXD_IPSEC_ESP_LEN_MASK	0x000000FF
     89 
     90 #define IGC_RAR_ENTRIES_BASE		16
     91 
     92 /* Receive Descriptor - Advanced */
     93 union igc_adv_rx_desc {
     94 	struct {
     95 		uint64_t pkt_addr; /* Packet buffer address */
     96 		uint64_t hdr_addr; /* Header buffer address */
     97 	} read;
     98 	struct {
     99 		struct {
    100 			union {
    101 				uint32_t data;
    102 				struct {
    103 					uint16_t pkt_info; /* Pkt type */
    104 					/* Split Header, header buffer len */
    105 					uint16_t hdr_info;
    106 				} hs_rss;
    107 			} lo_dword;
    108 			union {
    109 				uint32_t rss; /* RSS hash */
    110 				struct {
    111 					uint16_t ip_id; /* IP id */
    112 					uint16_t csum; /* Packet checksum */
    113 				} csum_ip;
    114 			} hi_dword;
    115 		} lower;
    116 		struct {
    117 			uint32_t status_error; /* ext status/error */
    118 			uint16_t length; /* Packet length */
    119 			uint16_t vlan; /* VLAN tag */
    120 		} upper;
    121 	} wb;  /* writeback */
    122 };
    123 
    124 /* Additional Transmit Descriptor Control definitions */
    125 #define IGC_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
    126 
    127 /* Additional Receive Descriptor Control definitions */
    128 #define IGC_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
    129 
    130 /* SRRCTL bit definitions */
    131 #define IGC_SRRCTL_BSIZEPKT_SHIFT	10	/* Shift _right_ */
    132 #define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT	2	/* Shift _left_ */
    133 #define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
    134 
    135 #endif /* _IGC_BASE_H_ */
    136