| /src/sys/arch/bebox/stand/boot/ |
| ns16550.h | 50 #define iir fcr macro
|
| /src/sys/arch/prep/stand/boot/ |
| ns16550.h | 49 #define iir fcr macro
|
| /src/sys/arch/rs6000/stand/boot/ |
| ns16550.h | 49 #define iir fcr macro
|
| /src/sys/external/bsd/drm/dist/shared-core/ |
| i915_irq.c | 39 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
187 u32 iir; local
192 iir = I915_READ(IIR);
193 if (!iir)
199 * Clear the PIPE(A|B)STAT regs before the IIR
201 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
208 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
215 I915_WRITE(IIR, iir);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| interrupt.c | 47 #define iir_to_regbase(iir) (iir - 0x8)
275 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler
281 * This function is used to emulate the generic IIR register behavior.
292 u32 iir = *(u32 *)p_data; local
294 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
295 (vgpu_vreg(vgpu, reg) ^ iir));
300 vgpu_vreg(vgpu, reg) &= ~iir;
367 u32 iir = regbase_to_iir local
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/lm32/ |
| dv-lm32uart.c | 39 unsigned char iir; member in struct:lm32uart
101 uart->iir = MICOUART_IIR_TXRDY;
156 uart->iir &= ~MICOUART_IIR_TXRDY;
169 uart->iir |= MICOUART_IIR_TXRDY;
178 uart->iir = value;
228 value = uart->iir;
309 uart->iir = 0;
|
| /src/external/gpl3/gdb/dist/sim/lm32/ |
| dv-lm32uart.c | 39 unsigned char iir; member in struct:lm32uart
101 uart->iir = MICOUART_IIR_TXRDY;
156 uart->iir &= ~MICOUART_IIR_TXRDY;
169 uart->iir |= MICOUART_IIR_TXRDY;
178 uart->iir = value;
228 value = uart->iir;
309 uart->iir = 0;
|
| /src/sys/arch/hp300/dev/ |
| dnkbd.c | 879 uint8_t iir, lsr, c; local
886 iir = bus_space_read_1(bst, bsh, com_iir);
888 switch (iir & IIR_IMASK) {
940 if (iir & IIR_NOPEND)
|
| /src/sys/arch/sandpoint/sandpoint/ |
| satmgr.c | 185 #define IIR 2
643 int iir; local
646 iir = CSR_READ(sc, IIR) & IIR_IMASK;
647 if (iir == IIR_NOPEND) {
652 switch (iir) {
664 iir = CSR_READ(sc, IIR) & IIR_IMASK;
665 } while (iir != IIR_NOPEND);
|
| /src/sys/dev/ic/ |
| com.c | 744 * IIR changes into the EFR if LCR is set to LCR_EERS
745 * on 16650s. We also know IIR != 0 at this point.
2388 u_char lsr, iir; local
2396 iir = CSR_READ_1(regsp, COM_REG_IIR);
2405 (iir & IIR_BUSY) == IIR_BUSY) {
2422 iir = CSR_READ_1(regsp, COM_REG_IIR);
2427 (iir & IIR_BUSY) == IIR_BUSY) {
2468 if (ISSET(iir, IIR_NOPEND)) {
2499 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY))
2570 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY)
[all...] |
| /src/external/gpl3/gdb.old/dist/gdb/ |
| ser-go32.c | 275 unsigned char iir, lsr, c;
292 iir = inb (port, com_iir) & IIR_IMASK;
293 switch (iir)
347 COUNT (iir);
274 unsigned char iir, lsr, c; local
|
| /src/external/gpl3/gdb/dist/gdb/ |
| ser-go32.c | 275 unsigned char iir, lsr, c;
292 iir = inb (port, com_iir) & IIR_IMASK;
293 switch (iir)
347 COUNT (iir);
274 unsigned char iir, lsr, c; local
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_irq.c | 178 i915_reg_t iir, i915_reg_t ier)
185 /* IIR can theoretically queue up two events. Be paranoid. */
186 intel_uncore_write(uncore, iir, 0xffffffff);
187 intel_uncore_posting_read(uncore, iir);
188 intel_uncore_write(uncore, iir, 0xffffffff);
189 intel_uncore_posting_read(uncore, iir);
199 /* IIR can theoretically queue up two events. Be paranoid. */
242 i915_reg_t iir)
244 gen3_assert_iir_is_zero(uncore, iir);
1301 u32 iir, u32 pipe_stats[I915_MAX_PIPES]
1537 u32 iir, gt_iir, pm_iir; local
1622 u32 master_ctl, iir; local
2255 u32 iir; local
2335 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); local
2436 u32 iir; local
3619 u16 iir; local
3720 u32 iir; local
3863 u32 iir; local
[all...] |
| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 221 iir: .equ 19 ; Interruption Instruction Register label
|
