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    Searched defs:imr (Results 1 - 22 of 22) sorted by relevancy

  /src/sys/arch/arm/at91/
at91spi.c 332 DPRINTFN(3, ("%s: dmaoffs=%d len=%d wchunk=%p (%p:%d) rchunk=%p (%p:%d) mr=%"PRIX32" sr=%"PRIX32" imr=%"PRIX32" csr0=%"PRIX32"\n",
422 uint32_t imr, sr; local in function:at91spi_intr
425 if ((imr = GETREG(sc, SPI_IMR)) == 0) {
432 if (!(sr & imr)) {
434 DPRINTFN(3, ("%s: interrupts are not enabled, sr=%08"PRIX32" imr=%08"PRIX32"\n",
435 __FUNCTION__, sr, imr));
439 DPRINTFN(3, ("%s: sr=%08"PRIX32" imr=%08"PRIX32"\n",
440 __FUNCTION__, sr, imr));
442 if (sr & imr & SPI_SR_MODF) {
447 if (sr & imr & SPI_SR_OVRES)
    [all...]
at91twi.c 146 u_int sr, isr, imr; local in function:at91twi_intr
149 imr = at91twi_readreg(sc, TWI_IMR);
150 isr = sr & imr;
154 // printf("%s(%s): interrupts are disabled (sr=%08X imr=%08X)\n", __FUNCTION__, device_xname(sc->sc_dev), sr, imr);
at91emac.c 219 uint32_t imr, isr, ctl; local in function:emac_intr
222 imr = ~EMAC_READ(ETH_IMR);
223 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE
229 isr = EMAC_READ(ETH_ISR) & imr;
235 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__,
236 isr, rsr, imr));
at91dbgu.c 1042 uint32_t imr, sr; local in function:dbgu_intr
1044 imr = DBGUREG(DBGU_IMR);
1046 if (!imr)
1050 if (!(sr & imr)) {
1052 // printf("sr=0x%08x imr=0x%08x\n", sr, imr);
1130 rnd_add_uint32(&sc->rnd_source, imr ^ sr ^ c);
at91usart.c 1096 u_int csr, imr; local in function:at91usart_intr
1099 imr = at91usart_readreg(sc, US_IMR);
1100 if (!imr)
1104 DPRINTFN(6,("%s: csr=%08X imr=%08X\n", device_xname(sc->sc_dev), csr, imr));
1105 if (!ISSET(csr, imr))
  /src/sys/arch/evbmips/loongson/
loongson_intr.c 143 uint32_t isr0, isr, imr; local in function:evbmips_iointr
151 imr = REGVAL(BONITO_INTEN);
154 isr = isr0 & imr & LOONGSON_INTRMASK_LVL4;
yeeloong_machdep.c 373 uint imr; local in function:lemote_isa_intr_establish
380 imr = lemote_get_isa_imr();
381 imr |= (1 << irq);
382 DPRINTF(("lemote_isa_intr_establish: enable irq %d 0x%x\n", irq, imr));
383 loongson_set_isa_imr(imr);
430 uint32_t isr, imr, mask; local in function:lemote_isa_intr
434 imr = lemote_get_isa_imr();
435 isr = lemote_get_isa_isr() & imr;
474 loongson_set_isa_imr(imr);
generic2e_machdep.c 249 uint imr; local in function:generic2e_isa_intr_establish
255 imr = loongson_isaimr;
256 imr |= (1 << irq);
257 loongson_set_isa_imr(imr);
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
interrupt.c 167 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler
173 * This function is used to emulate the generic IMR register bit change
185 u32 imr = *(u32 *)p_data; local in function:intel_vgpu_reg_imr_handler
187 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
188 (vgpu_vreg(vgpu, reg) ^ imr));
190 vgpu_vreg(vgpu, reg) = imr;
369 u32 imr = regbase_to_imr( local in function:update_upstream_irq
372 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
  /src/sys/arch/evbmips/sbmips/
sb1250_icu.c 77 /* imr values corresponding to each pin */
275 vaddr_t imr = MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK); local in function:sb1250_icu_init
276 for (u_int i = 1; imr += IMR_REGISTER_SPACING, i < cpus; i++) {
277 WRITE_REG(imr, imr_all);
  /src/sys/arch/sbmips/sbmips/
sb1250_icu.c 77 /* imr values corresponding to each pin */
275 vaddr_t imr = MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK); local in function:sb1250_icu_init
276 for (u_int i = 1; imr += IMR_REGISTER_SPACING, i < cpus; i++) {
277 WRITE_REG(imr, imr_all);
  /src/sys/net80211/
ieee80211.c 383 struct ifmediareq imr; local in function:ieee80211_media_init_with_lock
477 ieee80211_media_status(ifp, &imr);
478 ifmedia_set(&ic->ic_media, imr.ifm_active);
743 ieee80211_media_status(struct ifnet *ifp, struct ifmediareq *imr)
753 imr->ifm_status = IFM_AVALID;
754 imr->ifm_active = IFM_IEEE80211;
756 imr->ifm_status |= IFM_ACTIVE;
765 imr->ifm_active |= ieee80211_rate2media(ic,
772 imr->ifm_active |= ieee80211_rate2media(ic,
775 imr->ifm_active |= IFM_AUTO
    [all...]
  /src/sys/dev/cadence/
if_cemac.c 258 uint32_t imr, isr, ctl; local in function:cemac_intr
270 imr = ~CEMAC_READ(ETH_IMR);
271 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE |
280 isr &= imr;
290 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__,
291 isr, rsr, imr));
  /src/sys/arch/sgimips/dev/
scnvar.h 104 u_char imr; /* IMR bits */ member in struct:duart
  /src/sys/arch/zaurus/zaurus/
machdep.c 577 uint16_t mcr, cdr, csr, cpr, ccr, irr, irm, imr, isr; local in function:hw_isc1000
587 imr = ioreg16_read(baseaddr + SCOOP_IMR);
594 irr == 0 && irm == 0 && imr == 0 && isr == 0 &&
  /src/sys/arch/hppa/dev/
mongoose.c 283 volatile uint8_t *imr, *pic; local in function:mg_intr_establish
307 imr = &sc->sc_ctrl->imr0;
310 imr = &sc->sc_ctrl->imr1;
315 *imr |= 1 << irq;
329 volatile uint8_t *imr; local in function:mg_intr_disestablish
337 imr = &sc->sc_ctrl->imr0;
339 imr = &sc->sc_ctrl->imr1;
340 *imr &= ~(1 << irq);
dino.c 70 uint32_t imr; /* 0x018 rw intr mask reg */ member in struct:dino_regs
1786 r->imr = 0;
1793 sc->sc_ir.ir_mask = &r->imr;
  /src/sys/dev/pci/
if_msk.c 2540 uint32_t imr, imtimer_ticks; local in function:msk_init
2636 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
2637 if (imr != SK_IM_USECS(sc->sk_int_mod)) {
if_txp.c 441 uint32_t r, i, ier, imr; local in function:txp_download_fw
446 imr = READ_REG(sc, TXP_IMR);
447 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
511 WRITE_REG(sc, TXP_IMR, imr);
if_sk.c 2733 uint32_t imr, imtimer_ticks; local in function:sk_init
2850 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
2851 if (imr != SK_IM_USECS(sc->sk_int_mod)) {
  /src/sys/arch/arm/rockchip/
rk_spi.c 407 uint32_t imr = SPI_IMR_RFOIM | SPI_IMR_RFUIM | SPI_IMR_TFOIM; local in function:rk_spi_set_interrupt_mask
418 imr |= SPI_IMR_RFFIM;
429 imr |= SPI_IMR_TFEIM;
433 if (!ISSET(imr, (SPI_IMR_RFFIM | SPI_IMR_TFEIM))) {
435 imr |= SPI_IMR_TFEIM;
438 SPIREG_WRITE(sc, SPI_IMR, imr);
  /src/sys/external/mit/xen-include-public/dist/xen/include/public/arch-x86/hvm/
save.h 312 uint8_t imr; member in struct:hvm_hw_vpic

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