1 /* $NetBSD: octeon_iobus.c,v 1.7 2021/08/07 16:18:59 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2007 5 * Internet Initiative Japan, Inc. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: octeon_iobus.c,v 1.7 2021/08/07 16:18:59 thorpej Exp $"); 31 32 #include "locators.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 38 #define _MIPS_BUS_DMA_PRIVATE 39 #include <sys/bus.h> 40 41 #include <mips/cavium/include/iobusvar.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 struct iobus_softc { 46 device_t sc_dev; 47 48 /* XXX load/IOBDMA/store operations */ 49 bus_space_handle_t sc_ops_bush; 50 }; 51 52 static int iobus_match(device_t, struct cfdata *, void *); 53 static void iobus_attach(device_t, device_t, void *); 54 static int iobus_submatch(device_t, struct cfdata *, const int *, void *); 55 static int iobus_print(void *, const char *); 56 static void iobus_init(struct iobus_softc *); 57 static void iobus_init_map(struct iobus_softc *); 58 static void iobus_init_local(struct iobus_softc *); 59 static void iobus_init_local_pow(struct iobus_softc *); 60 static void iobus_init_local_fpa(struct iobus_softc *); 61 62 static void iobus_bus_io_init(bus_space_tag_t, void *); 63 64 static struct mips_bus_space *iobus_bust; 65 static struct mips_bus_dma_tag *iobus_dmat; 66 67 void 68 iobus_bootstrap(struct octeon_config *mcp) 69 { 70 iobus_bus_io_init(&mcp->mc_iobus_bust, mcp); 71 72 iobus_bust = &mcp->mc_iobus_bust; 73 iobus_dmat = &mcp->mc_iobus_dmat; 74 } 75 76 /* ---- autoconf */ 77 78 CFATTACH_DECL_NEW(iobus, sizeof(struct iobus_softc), 79 iobus_match, iobus_attach, NULL, NULL); 80 81 static int 82 iobus_match(device_t parent, struct cfdata *match, void *aux) 83 { 84 return 1; 85 } 86 87 static void 88 iobus_attach(device_t parent, device_t self, void *aux) 89 { 90 struct iobus_softc *sc = device_private(self); 91 const struct iobus_dev *dev; 92 struct iobus_attach_args aa; 93 const bool fdt_p = fdtbus_get_data() != NULL; 94 int i, j; 95 96 sc->sc_dev = self; 97 98 aprint_normal("\n"); 99 100 iobus_init(sc); 101 102 /* XXX should only attach Octeon 1 and Octeon Plus drivers */ 103 for (i = 0; i < (int)iobus_ndevs; i++) { 104 dev = iobus_devs[i]; 105 for (j = 0; j < dev->nunits; j++) { 106 if (fdt_p && (dev->flags & IOBUS_DEV_FDT) == 0) 107 continue; 108 109 aa.aa_name = dev->name; 110 aa.aa_unitno = j; 111 aa.aa_unit = &dev->units[j]; 112 aa.aa_bust = iobus_bust; 113 aa.aa_dmat = iobus_dmat; 114 115 config_found(self, &aa, iobus_print, 116 CFARGS(.submatch = iobus_submatch)); 117 } 118 } 119 } 120 121 static int 122 iobus_submatch(device_t parent, struct cfdata *cf, const int *ldesc, void *aux) 123 { 124 125 return config_match(parent, cf, aux); 126 } 127 128 static int 129 iobus_print(void *aux, const char *pnp) 130 { 131 struct iobus_attach_args *aa = aux; 132 133 if (pnp) 134 aprint_normal("%s at %s", aa->aa_name, pnp); 135 136 aprint_normal(" address 0x%016" PRIx64, aa->aa_unit->addr); 137 138 return UNCONF; 139 } 140 141 /* ---- */ 142 143 void 144 iobus_init(struct iobus_softc *sc) 145 { 146 147 iobus_init_map(sc); 148 iobus_init_local(sc); 149 } 150 151 void 152 iobus_init_map(struct iobus_softc *sc) 153 { 154 155 /* XXX map all ``operations'' space at once */ 156 bus_space_map( 157 iobus_bust, 158 0x0001280000000000ULL, 159 0x0001800000000000ULL - 0x0001280000000000ULL, 160 0, 161 &sc->sc_ops_bush); 162 } 163 164 void 165 iobus_init_local(struct iobus_softc *sc) 166 { 167 168 iobus_init_local_pow(sc); 169 iobus_init_local_fpa(sc); 170 } 171 172 extern struct octeon_config octeon_configuration; 173 174 void 175 iobus_init_local_pow(struct iobus_softc *sc) 176 { 177 178 void octpow_bootstrap(struct octeon_config *); 179 180 aprint_normal("%s: initializing POW\n", device_xname(sc->sc_dev)); 181 182 octpow_bootstrap(&octeon_configuration); 183 } 184 185 void 186 iobus_init_local_fpa(struct iobus_softc *sc) 187 { 188 189 void octfpa_bootstrap(struct octeon_config *); 190 191 aprint_normal("%s: initializing FPA\n", device_xname(sc->sc_dev)); 192 193 octfpa_bootstrap(&octeon_configuration); 194 } 195 196 /* ---- bus_space(9) */ 197 198 #define CHIP iobus 199 #define CHIP_IO 200 #define CHIP_ACCESS_SIZE 8 201 202 /* CIU and GPIO NCB type CSRs */ 203 #define CHIP_W1_BUS_START(v) 0x0001070000000000ULL 204 #define CHIP_W1_BUS_END(v) 0x00010700ffffffffULL 205 #define CHIP_W1_SYS_START(v) 0x8001070000000000ULL 206 #define CHIP_W1_SYS_END(v) 0x80010700ffffffffULL 207 208 /* a number of RSL type CSRs */ 209 #define CHIP_W2_BUS_START(v) 0x0001180000000000ULL 210 #define CHIP_W2_BUS_END(v) 0x000118ffffffffffULL 211 #define CHIP_W2_SYS_START(v) 0x8001180000000000ULL 212 #define CHIP_W2_SYS_END(v) 0x800118ffffffffffULL 213 214 /* load/IOBDMA/store operations */ 215 #define CHIP_W3_BUS_START(v) 0x0001280000000000ULL 216 #define CHIP_W3_BUS_END(v) 0x00017fffffffffffULL 217 #define CHIP_W3_SYS_START(v) 0x8001280000000000ULL 218 #define CHIP_W3_SYS_END(v) 0x80017fffffffffffULL 219 220 #include <mips/mips/bus_space_alignstride_chipdep.c> 221
Indexes created Tue Sep 23 13:09:54 GMT 2025