1 /* $NetBSD: iomdiic.c,v 1.13 2025/09/15 13:23:01 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/device.h> 40 #include <sys/device_impl.h> /* XXX autoconf abuse */ 41 #include <sys/kernel.h> 42 #include <sys/systm.h> 43 #include <sys/mutex.h> 44 #include <sys/bus.h> 45 #include <sys/cpu.h> 46 47 #include <arm/iomd/iomdreg.h> 48 #include <arm/iomd/iomdvar.h> 49 50 #include <dev/i2c/i2cvar.h> 51 #include <dev/i2c/i2c_bitbang.h> 52 53 #include <arm/iomd/iomdiicvar.h> 54 55 struct iomdiic_softc { 56 device_t sc_dev; 57 bus_space_tag_t sc_st; 58 bus_space_handle_t sc_sh; 59 60 struct i2c_controller sc_i2c; 61 62 /* 63 * The SDA pin is open-drain, so we make it an input by 64 * writing a 1 to it. 65 */ 66 uint8_t sc_iomd_iocr; 67 }; 68 69 static int iomdiic_send_start(void *, int); 70 static int iomdiic_send_stop(void *, int); 71 static int iomdiic_initiate_xfer(void *, i2c_addr_t, int); 72 static int iomdiic_read_byte(void *, uint8_t *, int); 73 static int iomdiic_write_byte(void *, uint8_t, int); 74 75 #define IOMDIIC_READ *(volatile uint8_t *)(IOMD_ADDRESS(IOMD_IOCR)) 76 #define IOMDIIC_WRITE(x) *(volatile uint8_t *)(IOMD_ADDRESS(IOMD_IOCR)) = (x) 77 78 #define IOMD_IOCR_SDA 0x01 79 #define IOMD_IOCR_SCL 0x02 80 81 static void 82 iomdiic_bb_set_bits(void *cookie, uint32_t bits) 83 { 84 struct iomdiic_softc *sc = cookie; 85 86 IOMDIIC_WRITE((IOMDIIC_READ & ~(IOMD_IOCR_SDA|IOMD_IOCR_SCL)) | 87 sc->sc_iomd_iocr | bits); 88 } 89 90 static void 91 iomdiic_bb_set_dir(void *cookie, uint32_t bits) 92 { 93 struct iomdiic_softc *sc = cookie; 94 95 sc->sc_iomd_iocr = bits; 96 } 97 98 static uint32_t 99 iomdiic_bb_read_bits(void *cookie) 100 { 101 102 return (IOMDIIC_READ); 103 } 104 105 static const struct i2c_bitbang_ops iomdiic_bbops = { 106 iomdiic_bb_set_bits, 107 iomdiic_bb_set_dir, 108 iomdiic_bb_read_bits, 109 { 110 IOMD_IOCR_SDA, /* SDA */ 111 IOMD_IOCR_SCL, /* SCL */ 112 0, /* SDA is output */ 113 IOMD_IOCR_SDA, /* SDA is input */ 114 } 115 }; 116 117 static int 118 iomdiic_match(device_t parent, cfdata_t cf, void *aux) 119 { 120 struct iic_attach_args *ia = aux; 121 122 if (strcmp(ia->ia_name, "iic") == 0) return 1; 123 return 0; 124 } 125 126 static void 127 iomdiic_attach(device_t parent, device_t self, void *aux) 128 { 129 struct iomdiic_softc *sc = device_private(self); 130 131 aprint_normal("\n"); 132 133 sc->sc_dev = self; 134 135 iic_tag_init(&sc->sc_i2c); 136 sc->sc_i2c.ic_cookie = sc; 137 sc->sc_i2c.ic_send_start = iomdiic_send_start; 138 sc->sc_i2c.ic_send_stop = iomdiic_send_stop; 139 sc->sc_i2c.ic_initiate_xfer = iomdiic_initiate_xfer; 140 sc->sc_i2c.ic_read_byte = iomdiic_read_byte; 141 sc->sc_i2c.ic_write_byte = iomdiic_write_byte; 142 143 iicbus_attach(sc->sc_dev, &sc->sc_i2c); 144 } 145 146 CFATTACH_DECL_NEW(iomdiic, sizeof(struct iomdiic_softc), 147 iomdiic_match, iomdiic_attach, NULL, NULL); 148 149 i2c_tag_t 150 iomdiic_bootstrap_cookie(void) 151 { 152 static struct iomdiic_softc sc; 153 static struct device dev; 154 155 /* XXX Yuck. */ 156 strcpy(dev.dv_xname, "iomdiicboot"); 157 158 sc.sc_dev = &dev; 159 160 iic_tag_init(&sc.sc_i2c); 161 sc.sc_i2c.ic_cookie = ≻ 162 sc.sc_i2c.ic_send_start = iomdiic_send_start; 163 sc.sc_i2c.ic_send_stop = iomdiic_send_stop; 164 sc.sc_i2c.ic_initiate_xfer = iomdiic_initiate_xfer; 165 sc.sc_i2c.ic_read_byte = iomdiic_read_byte; 166 sc.sc_i2c.ic_write_byte = iomdiic_write_byte; 167 168 return ((void *) &sc.sc_i2c); 169 } 170 171 static int 172 iomdiic_send_start(void *cookie, int flags) 173 { 174 175 return (i2c_bitbang_send_start(cookie, flags, &iomdiic_bbops)); 176 } 177 178 static int 179 iomdiic_send_stop(void *cookie, int flags) 180 { 181 182 return (i2c_bitbang_send_stop(cookie, flags, &iomdiic_bbops)); 183 } 184 185 static int 186 iomdiic_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 187 { 188 189 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &iomdiic_bbops)); 190 } 191 192 static int 193 iomdiic_read_byte(void *cookie, uint8_t *bytep, int flags) 194 { 195 196 return (i2c_bitbang_read_byte(cookie, bytep, flags, &iomdiic_bbops)); 197 } 198 199 static int 200 iomdiic_write_byte(void *cookie, uint8_t byte, int flags) 201 { 202 203 return (i2c_bitbang_write_byte(cookie, byte, flags, &iomdiic_bbops)); 204 } 205
Indexes created Thu Sep 25 08:09:54 GMT 2025