| /src/sys/arch/arm/gemini/ |
| gemini_icu.c | 121 geminiicu_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
124 KASSERT(irqbase == 0 && (irq_mask & sc->sc_enabled_mask) == 0);
125 sc->sc_enabled_mask |= irq_mask;
131 if (irq_mask & sc->sc_level_mask)
133 irq_mask & sc->sc_level_mask);
137 geminiicu_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
142 sc->sc_enabled_mask &= ~irq_mask;
148 if (irq_mask & sc->sc_edge_mask)
150 irq_mask & sc->sc_edge_mask);
195 const uint32_t irq_mask = __BIT(is->is_irq) local in function:geminiicu_establish_irq
[all...] |
| gemini_gpio.c | 111 gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
116 gpio->gpio_enable_mask |= irq_mask;
122 if (irq_mask & gpio->gpio_level_mask)
124 irq_mask & gpio->gpio_level_mask);
128 gpio_pic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
133 gpio->gpio_enable_mask &= ~irq_mask;
134 GPIO_WRITE(gpio, GEMINI_GPIO_INTRENB, ~irq_mask);
139 if (irq_mask & gpio->gpio_edge_mask)
141 irq_mask & gpio->gpio_edge_mask);
168 uint32_t irq_mask = __BIT(is->is_irq) local in function:gpio_pic_establish_irq
[all...] |
| /src/sys/arch/arm/imx/ |
| imxgpio.c | 89 imxgpio_pic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
94 gpio->gpio_enable_mask |= irq_mask;
96 GPIO_WRITE(gpio, GPIO_ISR, irq_mask);
101 imxgpio_pic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
106 gpio->gpio_enable_mask &= ~irq_mask;
180 uint32_t irq_mask = __BIT(is->is_irq); local in function:imxgpio_pic_establish_irq
188 gpio->gpio_enable_mask &= ~irq_mask;
189 GPIO_WRITE(gpio, GPIO_ISR, irq_mask);
211 v &= ~irq_mask;
218 gpio->gpio_edge_mask |= irq_mask;
[all...] |
| imx31_gpio.c | 97 gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
102 gpio->gpio_enable_mask |= irq_mask;
107 if (irq_mask & gpio->gpio_level_mask)
108 GPIO_WRITE(gpio, GPIO_ISR, irq_mask);
113 gpio_pic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
118 gpio->gpio_enable_mask &= ~irq_mask;
172 uint32_t irq_mask = __BIT(is->is_irq); local in function:gpio_pic_establish_irq
180 gpio->gpio_enable_mask &= ~irq_mask;
182 GPIO_WRITE(gpio, GPIO_ISR, irq_mask);
204 v &= ~irq_mask;
[all...] |
| /src/sys/external/bsd/drm/dist/shared-core/ |
| radeon_irq.c | 141 u32 irq_mask = RADEON_SW_INT_TEST; local in function:radeon_acknowledge_irqs
161 irq_mask |= R500_DISPLAY_INT_STATUS;
163 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
165 irqs &= irq_mask;
|
| /src/sys/arch/acorn32/podulebus/ |
| rapide.c | 157 u_int irq_mask; member in struct:__anon63076f770108
242 sc->sc_podule->irq_mask = IRQ_MASK;
290 rcp->rc_irqmask = rapide_info[channel].irq_mask;
|
| simide.c | 123 u_int irq_mask; member in struct:__anonb01bb07d0108
210 sc->sc_podule->irq_mask = STATUS_IRQ;
281 scp->sc_irqmask = simide_info[channel].irq_mask;
|
| /src/sys/arch/acorn32/include/ |
| podulebus_machdep.h | 62 u_int irq_mask; member in struct:__anon529cc25c0108
|
| /src/sys/arch/mips/cavium/ |
| octeon_intr.c | 371 const uint64_t irq_mask = __BIT(irq % 64); local in function:octeon_intr_establish
376 cpu->cpu_ip2_enable[bank] |= irq_mask;
383 cpu->cpu_ip3_enable[bank] |= irq_mask;
390 cpu->cpu_ip3_enable[bank] |= irq_mask;
400 cpu->cpu_ip4_enable[bank] |= irq_mask;
407 cpu->cpu_ip4_enable[bank] |= irq_mask;
434 const uint64_t irq_mask = ~__BIT(irq % 64); local in function:octeon_intr_disestablish
439 cpu->cpu_ip2_enable[bank] &= ~irq_mask;
448 cpu->cpu_ip3_enable[bank] &= ~irq_mask;
459 cpu->cpu_ip4_enable[bank] &= ~irq_mask;
[all...] |
| /src/sys/arch/mac68k/obio/ |
| esp.c | 185 uint8_t irq_mask; /* mask for clearing IRQ */ local in function:espattach
260 irq_mask = V2IF_SCSIIRQ;
279 irq_mask = 0;
343 if (irq_mask) {
345 via2_reg(vIFR) = irq_mask;
346 via2_reg(vIER) = 0x80 | irq_mask;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rs600.c | 739 uint32_t irq_mask = S_000044_SW_INT(1); local in function:rs600_irq_ack
780 return irqs & irq_mask;
|
| radeon_r100.c | 765 uint32_t irq_mask = RADEON_SW_INT_TEST | local in function:r100_irq_ack
772 return irqs & irq_mask;
|
| /src/sys/arch/arm/pic/ |
| pic.c | 317 uint32_t irq_mask; local in function:pic_find_pending_irqs_by_ipl
324 irq_mask = __BIT(irq);
335 ipl_irq_mask |= irq_mask;
337 pending &= ~irq_mask;
|
| /src/sys/arch/arm/amlogic/ |
| mesongx_mmc.c | 953 const uint32_t irq_mask = IRQ_EN_RESP_STATUS | local in function:mesongx_mmc_exec_command
972 MMC_WRITE(sc, SD_EMMC_IRQ_EN, val | irq_mask);
1031 MMC_WRITE(sc, SD_EMMC_IRQ_EN, val & ~irq_mask);
|
| /src/sys/arch/powerpc/booke/pci/ |
| pq3pci.c | 1196 uint32_t irq_mask = __BIT(irq & 31); local in function:pq3pci_msi_claim
1202 msig->msig_free_mask ^= irq_mask;
|
| /src/sys/dev/i2c/ |
| axppmic.c | 1178 uint8_t irq_mask, val; local in function:axppmic_attach
1251 irq_mask = 0;
1253 irq_mask |= c->poklirq.mask;
1255 irq_mask |= c->acinirq.mask;
1257 irq_mask |= c->vbusirq.mask;
1259 irq_mask |= c->battirq.mask;
1261 irq_mask |= c->chargeirq.mask;
1263 irq_mask |= c->chargestirq.mask;
1266 irq_mask, 0);
|
| /src/sys/external/bsd/drm2/dist/drm/vmwgfx/ |
| vmwgfx_drv.h | 559 uint32_t irq_mask; /* Updates protected by waiter_lock */ member in struct:vmw_private
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_drv.h | 998 u32 irq_mask; member in union:drm_i915_private::__anon6c72b20e0e0a
|
