1 /* $NetBSD: gemini_gpio.c,v 1.5 2021/08/07 16:18:44 thorpej Exp $ */ 2 3 /* adapted from 4 * $NetBSD: omap2_gpio.c,v 1.6 2008/11/19 06:26:27 matt Exp 5 */ 6 7 /*- 8 * Copyright (c) 2007 The NetBSD Foundation, Inc. 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Matt Thomas 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: gemini_gpio.c,v 1.5 2021/08/07 16:18:44 thorpej Exp $"); 37 38 #define _INTR_PRIVATE 39 40 #include "locators.h" 41 #include "gpio.h" 42 #include "geminigmac.h" 43 #include "opt_gemini.h" 44 45 #include <sys/param.h> 46 #include <sys/evcnt.h> 47 #include <sys/atomic.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <machine/intr.h> 52 53 #include <arm/cpu.h> 54 #include <arm/armreg.h> 55 #include <arm/cpufunc.h> 56 57 #include <sys/bus.h> 58 59 #include <arm/gemini/gemini_reg.h> 60 #include <arm/gemini/gemini_obiovar.h> 61 #include <arm/gemini/gemini_gpiovar.h> 62 #include <arm/pic/picvar.h> 63 64 #if NGPIO > 0 65 #include <sys/gpio.h> 66 #include <dev/gpio/gpiovar.h> 67 #endif 68 69 static void gpio_pic_block_irqs(struct pic_softc *, size_t, uint32_t); 70 static void gpio_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t); 71 static int gpio_pic_find_pending_irqs(struct pic_softc *); 72 static void gpio_pic_establish_irq(struct pic_softc *, struct intrsource *); 73 74 const struct pic_ops gpio_pic_ops = { 75 .pic_block_irqs = gpio_pic_block_irqs, 76 .pic_unblock_irqs = gpio_pic_unblock_irqs, 77 .pic_find_pending_irqs = gpio_pic_find_pending_irqs, 78 .pic_establish_irq = gpio_pic_establish_irq, 79 }; 80 81 struct gpio_softc { 82 device_t gpio_dev; 83 struct pic_softc gpio_pic; 84 struct intrsource *gpio_is; 85 bus_space_tag_t gpio_memt; 86 bus_space_handle_t gpio_memh; 87 uint32_t gpio_enable_mask; 88 uint32_t gpio_edge_mask; 89 uint32_t gpio_edge_falling_mask; 90 uint32_t gpio_edge_rising_mask; 91 uint32_t gpio_level_mask; 92 uint32_t gpio_level_hi_mask; 93 uint32_t gpio_level_lo_mask; 94 uint32_t gpio_inuse_mask; 95 #if NGPIO > 0 96 struct gpio_chipset_tag gpio_chipset; 97 gpio_pin_t gpio_pins[32]; 98 #endif 99 }; 100 101 #define PIC_TO_SOFTC(pic) \ 102 ((struct gpio_softc *)((char *)(pic) - \ 103 offsetof(struct gpio_softc, gpio_pic))) 104 105 #define GPIO_READ(gpio, reg) \ 106 bus_space_read_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg)) 107 #define GPIO_WRITE(gpio, reg, val) \ 108 bus_space_write_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg), (val)) 109 110 void 111 gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 112 { 113 struct gpio_softc * const gpio = PIC_TO_SOFTC(pic); 114 KASSERT(irq_base == 0); 115 116 gpio->gpio_enable_mask |= irq_mask; 117 /* 118 * If this a level source, ack it now. If it's still asserted 119 * it'll come back. 120 */ 121 GPIO_WRITE(gpio, GEMINI_GPIO_INTRENB, gpio->gpio_enable_mask); 122 if (irq_mask & gpio->gpio_level_mask) 123 GPIO_WRITE(gpio, GEMINI_GPIO_INTRCLR, 124 irq_mask & gpio->gpio_level_mask); 125 } 126 127 void 128 gpio_pic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 129 { 130 struct gpio_softc * const gpio = PIC_TO_SOFTC(pic); 131 KASSERT(irq_base == 0); 132 133 gpio->gpio_enable_mask &= ~irq_mask; 134 GPIO_WRITE(gpio, GEMINI_GPIO_INTRENB, ~irq_mask); 135 /* 136 * If any of the sources are edge triggered, ack them now so 137 * we won't lose them. 138 */ 139 if (irq_mask & gpio->gpio_edge_mask) 140 GPIO_WRITE(gpio, GEMINI_GPIO_INTRCLR, 141 irq_mask & gpio->gpio_edge_mask); 142 } 143 144 int 145 gpio_pic_find_pending_irqs(struct pic_softc *pic) 146 { 147 struct gpio_softc * const gpio = PIC_TO_SOFTC(pic); 148 uint32_t pending; 149 150 pending = GPIO_READ(gpio, GEMINI_GPIO_INTRMSKSTATE); 151 KASSERT((pending & ~gpio->gpio_enable_mask) == 0); 152 if (pending == 0) 153 return 0; 154 155 /* 156 * Now find all the pending bits and mark them as pending. 157 */ 158 (void) pic_mark_pending_sources(&gpio->gpio_pic, 0, pending); 159 160 return 1; 161 } 162 163 void 164 gpio_pic_establish_irq(struct pic_softc *pic, struct intrsource *is) 165 { 166 struct gpio_softc * const gpio = PIC_TO_SOFTC(pic); 167 KASSERT(is->is_irq < 32); 168 uint32_t irq_mask = __BIT(is->is_irq); 169 uint32_t v; 170 #if 0 171 unsigned int i; 172 struct intrsource *maybe_is; 173 #endif 174 175 /* 176 * Make sure the irq isn't enabled and not asserting. 177 */ 178 gpio->gpio_enable_mask &= ~irq_mask; 179 GPIO_WRITE(gpio, GEMINI_GPIO_INTRENB, gpio->gpio_enable_mask); 180 GPIO_WRITE(gpio, GEMINI_GPIO_INTRCLR, irq_mask); 181 182 /* 183 * Convert the type to a gpio type and figure out which bits in what 184 * register we have to tweak. 185 */ 186 gpio->gpio_edge_rising_mask &= ~irq_mask; 187 gpio->gpio_edge_falling_mask &= ~irq_mask; 188 gpio->gpio_level_hi_mask &= ~irq_mask; 189 gpio->gpio_level_lo_mask &= ~irq_mask; 190 switch (is->is_type) { 191 case IST_LEVEL_LOW: gpio->gpio_level_lo_mask |= irq_mask; break; 192 case IST_LEVEL_HIGH: gpio->gpio_level_hi_mask |= irq_mask; break; 193 case IST_EDGE_FALLING: gpio->gpio_edge_falling_mask |= irq_mask; break; 194 case IST_EDGE_RISING: gpio->gpio_edge_rising_mask |= irq_mask; break; 195 case IST_EDGE_BOTH: 196 gpio->gpio_edge_rising_mask |= irq_mask; 197 gpio->gpio_edge_falling_mask |= irq_mask; 198 break; 199 default: 200 panic("%s: unknown is_type %d\n", __FUNCTION__, is->is_type); 201 } 202 gpio->gpio_edge_mask = 203 gpio->gpio_edge_rising_mask | gpio->gpio_edge_falling_mask; 204 gpio->gpio_level_mask = 205 gpio->gpio_level_hi_mask|gpio->gpio_level_lo_mask; 206 gpio->gpio_inuse_mask |= irq_mask; 207 208 /* 209 * Set the interrupt type. 210 */ 211 GPIO_WRITE(gpio, GEMINI_GPIO_INTRTRIG, gpio->gpio_level_mask); 212 GPIO_WRITE(gpio, GEMINI_GPIO_INTREDGEBOTH, 213 gpio->gpio_edge_rising_mask & gpio->gpio_edge_falling_mask); 214 GPIO_WRITE(gpio, GEMINI_GPIO_INTRDIR, 215 gpio->gpio_edge_falling_mask | gpio->gpio_level_lo_mask); 216 217 /* 218 * Mark it as input by clearning bit(s) in PINDIR reg 219 */ 220 v = GPIO_READ(gpio, GEMINI_GPIO_PINDIR); 221 v &= ~irq_mask; 222 GPIO_WRITE(gpio, GEMINI_GPIO_PINDIR, v); 223 #if 0 224 for (i = 0, maybe_is = NULL; i < 32; i++) { 225 if ((is = pic->pic_sources[i]) != NULL) { 226 if (maybe_is == NULL || is->is_ipl > maybe_is->is_ipl) 227 maybe_is = is; 228 } 229 } 230 if (maybe_is != NULL) { 231 is = gpio->gpio_is; 232 KASSERT(is != NULL); 233 is->is_ipl = maybe_is->is_ipl; 234 (*is->is_pic->pic_ops->pic_establish_irq)(is->is_pic, is); 235 } 236 #endif 237 } 238 239 static int gpio_match(device_t, cfdata_t, void *); 240 static void gpio_attach(device_t, device_t, void *); 241 242 CFATTACH_DECL_NEW(geminigpio, 243 sizeof(struct gpio_softc), 244 gpio_match, gpio_attach, 245 NULL, NULL); 246 247 #if NGPIO > 0 || NGEMINIGMAC > 0 248 249 int 250 geminigpio_pin_read(void *arg, int pin) 251 { 252 struct gpio_softc * const gpio = device_private(arg); 253 254 return (GPIO_READ(gpio, GEMINI_GPIO_DATAIN) >> pin) & 1; 255 } 256 257 void 258 geminigpio_pin_write(void *arg, int pin, int value) 259 { 260 struct gpio_softc * const gpio = device_private(arg); 261 uint32_t mask = 1 << pin; 262 263 if (value) 264 GPIO_WRITE(gpio, GEMINI_GPIO_DATASET, mask); 265 else 266 GPIO_WRITE(gpio, GEMINI_GPIO_DATACLR, mask); 267 } 268 269 void 270 geminigpio_pin_ctl(void *arg, int pin, int flags) 271 { 272 struct gpio_softc * const gpio = device_private(arg); 273 uint32_t mask = 1 << pin; 274 uint32_t old, new; 275 276 old = GPIO_READ(gpio, GEMINI_GPIO_PINDIR); 277 new = old; 278 switch (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 279 case GPIO_PIN_INPUT: new &= ~mask; break; 280 case GPIO_PIN_OUTPUT: new |= mask; break; 281 default: return; 282 } 283 if (old != new) 284 GPIO_WRITE(gpio, GEMINI_GPIO_PINDIR, new); 285 } 286 287 static void 288 gpio_defer(device_t self) 289 { 290 struct gpio_softc * const gpio = device_private(self); 291 struct gpio_chipset_tag * const gp = &gpio->gpio_chipset; 292 struct gpiobus_attach_args gba; 293 gpio_pin_t *pins; 294 uint32_t mask, dir, valueout, valuein; 295 int pin; 296 297 gp->gp_cookie = gpio->gpio_dev; 298 gp->gp_pin_read = geminigpio_pin_read; 299 gp->gp_pin_write = geminigpio_pin_write; 300 gp->gp_pin_ctl = geminigpio_pin_ctl; 301 302 gba.gba_gc = gp; 303 gba.gba_pins = gpio->gpio_pins; 304 gba.gba_npins = __arraycount(gpio->gpio_pins); 305 306 dir = GPIO_READ(gpio, GEMINI_GPIO_PINDIR); 307 valueout = GPIO_READ(gpio, GEMINI_GPIO_DATAOUT); 308 valuein = GPIO_READ(gpio, GEMINI_GPIO_DATAIN); 309 for (pin = 0, mask = 1, pins = gpio->gpio_pins; 310 pin < 32; pin++, mask <<= 1, pins++) { 311 pins->pin_num = pin; 312 if (gpio->gpio_inuse_mask & mask) 313 pins->pin_caps = GPIO_PIN_INPUT; 314 else 315 pins->pin_caps = GPIO_PIN_INPUT|GPIO_PIN_OUTPUT; 316 pins->pin_flags = 317 (dir & mask) ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; 318 pins->pin_state = 319 (((dir & mask) ? valueout : valuein) & mask) 320 ? GPIO_PIN_HIGH 321 : GPIO_PIN_LOW; 322 } 323 324 config_found(self, &gba, gpiobus_print, CFARGS_NONE); 325 } 326 #endif /* NGPIO > 0 */ 327 328 int 329 gpio_match(device_t parent, cfdata_t cfdata, void *aux) 330 { 331 struct obio_attach_args *oa = aux; 332 333 if (oa->obio_addr == GEMINI_GPIO0_BASE 334 || oa->obio_addr == GEMINI_GPIO1_BASE 335 || oa->obio_addr == GEMINI_GPIO2_BASE) 336 return 1; 337 338 return 0; 339 } 340 341 void 342 gpio_attach(device_t parent, device_t self, void *aux) 343 { 344 struct obio_attach_args * const oa = aux; 345 struct gpio_softc * const gpio = device_private(self); 346 int error; 347 348 if (oa->obio_intr == OBIOCF_INTR_DEFAULT) 349 panic("\n%s: no intr assigned", device_xname(self)); 350 351 if (oa->obio_size == OBIOCF_SIZE_DEFAULT) 352 oa->obio_size = GEMINI_GPIO_SIZE; 353 354 gpio->gpio_dev = self; 355 gpio->gpio_memt = oa->obio_iot; 356 error = bus_space_map(oa->obio_iot, oa->obio_addr, oa->obio_size, 357 0, &gpio->gpio_memh); 358 359 if (error) { 360 aprint_error(": failed to map register %#lx@%#lx: %d\n", 361 oa->obio_size, oa->obio_addr, error); 362 return; 363 } 364 365 if (oa->obio_intrbase != OBIOCF_INTRBASE_DEFAULT) { 366 gpio->gpio_pic.pic_ops = &gpio_pic_ops; 367 strlcpy(gpio->gpio_pic.pic_name, device_xname(self), 368 sizeof(gpio->gpio_pic.pic_name)); 369 gpio->gpio_pic.pic_maxsources = 32; 370 pic_add(&gpio->gpio_pic, oa->obio_intrbase); 371 aprint_normal(": interrupts %d..%d", 372 oa->obio_intrbase, oa->obio_intrbase + 31); 373 gpio->gpio_is = intr_establish(oa->obio_intr, 374 IPL_HIGH, IST_LEVEL_HIGH, pic_handle_intr, &gpio->gpio_pic); 375 KASSERT(gpio->gpio_is != NULL); 376 aprint_normal(", intr %d", oa->obio_intr); 377 } 378 aprint_normal("\n"); 379 #if NGPIO > 0 380 config_interrupts(self, gpio_defer); 381 #endif 382 } 383
Indexes created Sat Sep 20 22:09:52 GMT 2025