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      1 /*
      2  * Copyright 2017 Intel Corporation
      3  *
      4  *  Permission is hereby granted, free of charge, to any person obtaining a
      5  *  copy of this software and associated documentation files (the "Software"),
      6  *  to deal in the Software without restriction, including without limitation
      7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8  *  and/or sell copies of the Software, and to permit persons to whom the
      9  *  Software is furnished to do so, subject to the following conditions:
     10  *
     11  *  The above copyright notice and this permission notice (including the next
     12  *  paragraph) shall be included in all copies or substantial portions of the
     13  *  Software.
     14  *
     15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
     21  *  IN THE SOFTWARE.
     22  */
     23 
     24 #include <assert.h>
     25 #include <stdlib.h>
     26 
     27 #include "drm-uapi/drm_fourcc.h"
     28 #include "drm-uapi/i915_drm.h"
     29 
     30 #include "isl.h"
     31 #include "dev/intel_device_info.h"
     32 #include "dev/intel_debug.h"
     33 
     34 uint32_t
     35 isl_tiling_to_i915_tiling(enum isl_tiling tiling)
     36 {
     37    switch (tiling) {
     38    case ISL_TILING_LINEAR:
     39       return I915_TILING_NONE;
     40 
     41    case ISL_TILING_X:
     42       return I915_TILING_X;
     43 
     44    case ISL_TILING_Y0:
     45    case ISL_TILING_HIZ:
     46    case ISL_TILING_CCS:
     47       return I915_TILING_Y;
     48 
     49    case ISL_TILING_W:
     50    case ISL_TILING_Yf:
     51    case ISL_TILING_Ys:
     52    case ISL_TILING_4:
     53    case ISL_TILING_64:
     54    case ISL_TILING_GFX12_CCS:
     55       return I915_TILING_NONE;
     56    }
     57 
     58    unreachable("Invalid ISL tiling");
     59 }
     60 
     61 enum isl_tiling
     62 isl_tiling_from_i915_tiling(uint32_t tiling)
     63 {
     64    switch (tiling) {
     65    case I915_TILING_NONE:
     66       return ISL_TILING_LINEAR;
     67 
     68    case I915_TILING_X:
     69       return ISL_TILING_X;
     70 
     71    case I915_TILING_Y:
     72       return ISL_TILING_Y0;
     73    }
     74 
     75    unreachable("Invalid i915 tiling");
     76 }
     77 
     78 /** Sentinel is DRM_FORMAT_MOD_INVALID. */
     79 const struct isl_drm_modifier_info
     80 isl_drm_modifier_info_list[] = {
     81    {
     82       .modifier = DRM_FORMAT_MOD_NONE,
     83       .name = "DRM_FORMAT_MOD_NONE",
     84       .tiling = ISL_TILING_LINEAR,
     85    },
     86    {
     87       .modifier = I915_FORMAT_MOD_X_TILED,
     88       .name = "I915_FORMAT_MOD_X_TILED",
     89       .tiling = ISL_TILING_X,
     90    },
     91    {
     92       .modifier = I915_FORMAT_MOD_Y_TILED,
     93       .name = "I915_FORMAT_MOD_Y_TILED",
     94       .tiling = ISL_TILING_Y0,
     95    },
     96    {
     97       .modifier = I915_FORMAT_MOD_Y_TILED_CCS,
     98       .name = "I915_FORMAT_MOD_Y_TILED_CCS",
     99       .tiling = ISL_TILING_Y0,
    100       .aux_usage = ISL_AUX_USAGE_CCS_E,
    101       .supports_clear_color = false,
    102    },
    103    {
    104       .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
    105       .name = "I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS",
    106       .tiling = ISL_TILING_Y0,
    107       .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E,
    108       .supports_clear_color = false,
    109    },
    110    {
    111       .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
    112       .name = "I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS",
    113       .tiling = ISL_TILING_Y0,
    114       .aux_usage = ISL_AUX_USAGE_MC,
    115       .supports_clear_color = false,
    116    },
    117    {
    118       .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
    119       .name = "I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC",
    120       .tiling = ISL_TILING_Y0,
    121       .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E,
    122       .supports_clear_color = true,
    123    },
    124    {
    125       .modifier = DRM_FORMAT_MOD_INVALID,
    126    },
    127 };
    128 
    129 const struct isl_drm_modifier_info *
    130 isl_drm_modifier_get_info(uint64_t modifier)
    131 {
    132    isl_drm_modifier_info_for_each(info) {
    133       if (info->modifier == modifier)
    134          return info;
    135    }
    136 
    137    return NULL;
    138 }
    139 
    140 uint32_t
    141 isl_drm_modifier_get_score(const struct intel_device_info *devinfo,
    142                            uint64_t modifier)
    143 {
    144    /* FINISHME: Add gfx12 modifiers */
    145    switch (modifier) {
    146    default:
    147       return 0;
    148    case DRM_FORMAT_MOD_LINEAR:
    149       return 1;
    150    case I915_FORMAT_MOD_X_TILED:
    151       return 2;
    152    case I915_FORMAT_MOD_Y_TILED:
    153       /* Gfx12.5 doesn't have Y-tiling. */
    154       if (devinfo->verx10 >= 125)
    155          return 0;
    156 
    157       return 3;
    158    case I915_FORMAT_MOD_Y_TILED_CCS:
    159       /* Gfx12's CCS layout differs from Gfx9-11. */
    160       if (devinfo->ver >= 12)
    161          return 0;
    162 
    163       if (INTEL_DEBUG(DEBUG_NO_RBC))
    164          return 0;
    165 
    166       return 4;
    167    }
    168 }
    169