1 /* $NetBSD: ixp12x0_pci.c,v 1.18 2022/09/27 06:36:42 skrll Exp $ */ 2 /* 3 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Ichiro FUKUHARA and Naoto Shimazaki. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ixp12x0_pci.c,v 1.18 2022/09/27 06:36:42 skrll Exp $"); 33 34 /* 35 * PCI configuration support for IXP12x0 Network Processor chip. 36 */ 37 38 #include "opt_pci.h" 39 #include "pci.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <arm/ixp12x0/ixp12x0reg.h> 48 #include <arm/ixp12x0/ixp12x0var.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pciconf.h> 53 54 #include <arm/locore.h> 55 56 void ixp12x0_pci_attach_hook(device_t, device_t, 57 struct pcibus_attach_args *); 58 int ixp12x0_pci_bus_maxdevs(void *, int); 59 pcitag_t ixp12x0_pci_make_tag(void *, int, int, int); 60 void ixp12x0_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 61 pcireg_t ixp12x0_pci_conf_read(void *, pcitag_t, int); 62 void ixp12x0_pci_conf_write(void *, pcitag_t, int, pcireg_t); 63 void ixp12x0_pci_conf_interrupt(void *, int, int, int, int, int *); 64 65 static vaddr_t ixp12x0_pci_conf_setup(void *, struct ixp12x0_softc *, pcitag_t, int); 66 67 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 68 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 69 70 #define MAX_PCI_DEVICES 4 71 72 /* 73 * IXM1200 PCI configuration Cycles 74 * Device Address 75 * ------------------------------------- 76 * 0 IXP1200 0x0800 - 0x08FF 77 * 1 i21555 0x1000 - 0x10FF 78 * 2 i82559 0x2000 - 0x20FF 79 * 3 PMC expansion 0x4000 - 0x40FF 80 */ 81 82 void 83 ixp12x0_pci_init(pci_chipset_tag_t pc, void *cookie) 84 { 85 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 86 struct ixp12x0_softc *sc = cookie; 87 #endif 88 pc->pc_conf_v = cookie; 89 pc->pc_attach_hook = ixp12x0_pci_attach_hook; 90 pc->pc_bus_maxdevs = ixp12x0_pci_bus_maxdevs; 91 pc->pc_make_tag = ixp12x0_pci_make_tag; 92 pc->pc_decompose_tag = ixp12x0_pci_decompose_tag; 93 pc->pc_conf_read = ixp12x0_pci_conf_read; 94 pc->pc_conf_write = ixp12x0_pci_conf_write; 95 pc->pc_conf_interrupt = ixp12x0_pci_conf_interrupt; 96 97 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 98 struct pciconf_resources *pcires = pciconf_resource_init(); 99 100 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 101 0, IXP12X0_PCI_IO_SIZE); 102 103 /* PCI MEM space is mapped same address as real memory */ 104 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 105 IXP12X0_PCI_MEM_HWBASE, IXP12X0_PCI_MEM_SIZE); 106 107 aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n"); 108 pci_configure_bus(pc, pcires, 0 /* XXX bus = 0 */, 109 arm_dcache_align); 110 111 pciconf_resource_fini(pcires); 112 #endif 113 } 114 115 void 116 ixp12x0_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p) 117 { 118 /* Nothing */ 119 } 120 121 void 122 ixp12x0_pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 123 { 124 /* Nothing to do. */ 125 } 126 127 int 128 ixp12x0_pci_bus_maxdevs(void *v, int busno) 129 { 130 return(MAX_PCI_DEVICES); 131 } 132 133 pcitag_t 134 ixp12x0_pci_make_tag(void *v, int bus, int device, int function) 135 { 136 #ifdef PCI_DEBUG 137 printf("ixp12x0_pci_make_tag(v=%p, bus=%d, device=%d, function=%d)\n", 138 v, bus, device, function); 139 #endif 140 return ((bus << 16) | (device << 11) | (function << 8)); 141 } 142 143 void 144 ixp12x0_pci_decompose_tag(void *v, pcitag_t tag, int *busp, int *devicep, int *functionp) 145 { 146 #ifdef PCI_DEBUG 147 printf("ixp12x0_pci_decompose_tag(v=%p, tag=0x%08lx, bp=%x, dp=%x, fp=%x)\n", 148 v, tag, (int)busp, (int)devicep, (int)functionp); 149 #endif 150 151 if (busp != NULL) 152 *busp = (tag >> 16) & 0xff; 153 if (devicep != NULL) 154 *devicep = (tag >> 11) & 0x1f; 155 if (functionp != NULL) 156 *functionp = (tag >> 8) & 0x7; 157 } 158 159 static vaddr_t 160 ixp12x0_pci_conf_setup(void *v, struct ixp12x0_softc *sc, pcitag_t tag, int offset) 161 { 162 int bus, device, function; 163 vaddr_t addr; 164 165 if ((unsigned int)offset >= PCI_CONF_SIZE) 166 return 0; 167 168 ixp12x0_pci_decompose_tag(v, tag, &bus, &device, &function); 169 170 if (bus == 0) { 171 /* configuration type 0 */ 172 addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) + 173 ((1 << (device + 10)) | (offset & ~3)); 174 } else { 175 /* configuration type 1 */ 176 addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf1_ioh) + 177 ((bus << 16) | (device << 11) | 178 (function << 8) | (offset & ~3) | 1); 179 } 180 return addr; 181 } 182 183 pcireg_t 184 ixp12x0_pci_conf_read(void *v, pcitag_t tag, int offset) 185 { 186 struct ixp12x0_softc *sc = v; 187 vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset); 188 pcireg_t rv; 189 int s; 190 191 #ifdef PCI_DEBUG 192 printf("ixp12x0_pci_conf_read: base=%lx,va=%lx,tag=%lx,offset=%x\n", 193 sc->sc_conf0_ioh, va, tag, offset); 194 #endif 195 if (va == 0) 196 return -1; 197 198 PCI_CONF_LOCK(s); 199 200 if (badaddr_read((void *) va, sizeof(rv), &rv)) { 201 #ifdef PCI_DEBUG 202 printf("conf_read: %lx bad address\n", va); 203 #endif 204 rv = (pcireg_t) - 1; 205 } 206 207 PCI_CONF_UNLOCK(s); 208 209 return rv; 210 } 211 212 void 213 ixp12x0_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 214 { 215 struct ixp12x0_softc *sc = v; 216 vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset); 217 int s; 218 219 #ifdef PCI_DEBUG 220 printf("ixp12x0_pci_conf_write: tag=%lx offset=%x -> va=%lx (base=%lx)\n", 221 tag, offset, va, sc->sc_conf0_ioh); 222 #endif 223 224 PCI_CONF_LOCK(s); 225 226 *(pcireg_t *) va = val; 227 228 PCI_CONF_UNLOCK(s); 229 } 230
Indexes created Sat Sep 27 22:09:54 GMT 2025