| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dsi.h | 72 unsigned int lane_count; member in struct:intel_dsi
|
| vlv_dsi.c | 48 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
52 8 * 100), lane_count);
56 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
59 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
1043 unsigned int lane_count = intel_dsi->lane_count; local in function:bxt_dsi_get_pipe_config
1092 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1094 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1096 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1146 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1238 unsigned int lane_count = intel_dsi->lane_count; local in function:set_dsi_timings
[all...] |
| intel_display_types.h | 943 u8 lane_count; member in struct:intel_crtc_state
1228 u8 lane_count; member in struct:intel_dp
|
| intel_dp.c | 427 u8 lane_count)
438 if (lane_count == 0 ||
439 lane_count > intel_dp_max_lane_count(intel_dp))
447 u8 lane_count)
454 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
462 int link_rate, u8 lane_count)
473 lane_count)) {
478 intel_dp->max_link_lane_count = lane_count;
479 } else if (lane_count > 1) {
483 lane_count >> 1))
2013 int bpp, clock, lane_count; local in function:intel_dp_compute_link_config_wide
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hwseq.c | 2217 enum dc_lane_count lane_count = local in function:dcn20_enable_stream
2218 pipe_ctx->stream->link->cur_link_settings.lane_count;
2248 if (lane_count != 0)
2249 early_control = active_total_with_borders % lane_count;
2252 early_control = lane_count;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_hw_sequencer.c | 659 enum dc_lane_count lane_count = local in function:dce110_enable_stream
660 pipe_ctx->stream->link->cur_link_settings.lane_count;
684 if (lane_count != 0)
685 early_control = active_total_with_borders % lane_count;
688 early_control = lane_count;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_dp.c | 145 lt_settings->link_settings.lane_count;
180 lt_settings->link_settings.lane_count,
190 lt_settings->link_settings.lane_count,
279 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
296 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
388 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
450 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
508 max_lt_setting->link_settings.lane_count =
509 link_training_setting->link_settings.lane_count;
514 link_training_setting->link_settings.lane_count;
744 enum dc_lane_count lane_count = local in function:perform_post_lt_adj_req_sequence
880 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; local in function:perform_channel_equalization_sequence
962 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; local in function:perform_clock_recovery_sequence
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_dp_types.h | 103 enum dc_lane_count lane_count; member in struct:dc_link_settings
|
