1 /* $NetBSD: vlv_dsi.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Author: Jani Nikula <jani.nikula (at) intel.com> 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: vlv_dsi.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $"); 30 31 #include <linux/slab.h> 32 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_mipi_dsi.h> 37 38 #include "i915_drv.h" 39 #include "intel_atomic.h" 40 #include "intel_connector.h" 41 #include "intel_display_types.h" 42 #include "intel_dsi.h" 43 #include "intel_fifo_underrun.h" 44 #include "intel_panel.h" 45 #include "intel_sideband.h" 46 47 /* return pixels in terms of txbyteclkhs */ 48 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 49 u16 burst_mode_ratio) 50 { 51 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 52 8 * 100), lane_count); 53 } 54 55 /* return pixels equvalent to txbyteclkhs */ 56 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 57 u16 burst_mode_ratio) 58 { 59 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 60 (bpp * burst_mode_ratio)); 61 } 62 63 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 64 { 65 /* It just so happens the VBT matches register contents. */ 66 switch (fmt) { 67 case VID_MODE_FORMAT_RGB888: 68 return MIPI_DSI_FMT_RGB888; 69 case VID_MODE_FORMAT_RGB666: 70 return MIPI_DSI_FMT_RGB666; 71 case VID_MODE_FORMAT_RGB666_PACKED: 72 return MIPI_DSI_FMT_RGB666_PACKED; 73 case VID_MODE_FORMAT_RGB565: 74 return MIPI_DSI_FMT_RGB565; 75 default: 76 MISSING_CASE(fmt); 77 return MIPI_DSI_FMT_RGB666; 78 } 79 } 80 81 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 82 { 83 struct drm_encoder *encoder = &intel_dsi->base.base; 84 struct drm_device *dev = encoder->dev; 85 struct drm_i915_private *dev_priv = to_i915(dev); 86 u32 mask; 87 88 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 89 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 90 91 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), 92 mask, 100)) 93 DRM_ERROR("DPI FIFOs are not empty\n"); 94 } 95 96 static void write_data(struct drm_i915_private *dev_priv, 97 i915_reg_t reg, 98 const u8 *data, u32 len) 99 { 100 u32 i, j; 101 102 for (i = 0; i < len; i += 4) { 103 u32 val = 0; 104 105 for (j = 0; j < min_t(u32, len - i, 4); j++) 106 val |= *data++ << 8 * j; 107 108 I915_WRITE(reg, val); 109 } 110 } 111 112 static void read_data(struct drm_i915_private *dev_priv, 113 i915_reg_t reg, 114 u8 *data, u32 len) 115 { 116 u32 i, j; 117 118 for (i = 0; i < len; i += 4) { 119 u32 val = I915_READ(reg); 120 121 for (j = 0; j < min_t(u32, len - i, 4); j++) 122 *data++ = val >> 8 * j; 123 } 124 } 125 126 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 127 const struct mipi_dsi_msg *msg) 128 { 129 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 130 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; 131 struct drm_i915_private *dev_priv = to_i915(dev); 132 enum port port = intel_dsi_host->port; 133 struct mipi_dsi_packet packet; 134 ssize_t ret; 135 const u8 *header, *data; 136 i915_reg_t data_reg, ctrl_reg; 137 u32 data_mask, ctrl_mask; 138 139 ret = mipi_dsi_create_packet(&packet, msg); 140 if (ret < 0) 141 return ret; 142 143 header = packet.header; 144 data = packet.payload; 145 146 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 147 data_reg = MIPI_LP_GEN_DATA(port); 148 data_mask = LP_DATA_FIFO_FULL; 149 ctrl_reg = MIPI_LP_GEN_CTRL(port); 150 ctrl_mask = LP_CTRL_FIFO_FULL; 151 } else { 152 data_reg = MIPI_HS_GEN_DATA(port); 153 data_mask = HS_DATA_FIFO_FULL; 154 ctrl_reg = MIPI_HS_GEN_CTRL(port); 155 ctrl_mask = HS_CTRL_FIFO_FULL; 156 } 157 158 /* note: this is never true for reads */ 159 if (packet.payload_length) { 160 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 161 data_mask, 50)) 162 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); 163 164 write_data(dev_priv, data_reg, packet.payload, 165 packet.payload_length); 166 } 167 168 if (msg->rx_len) { 169 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); 170 } 171 172 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 173 ctrl_mask, 50)) { 174 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); 175 } 176 177 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); 178 179 /* ->rx_len is set only for reads */ 180 if (msg->rx_len) { 181 data_mask = GEN_READ_DATA_AVAIL; 182 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), 183 data_mask, 50)) 184 DRM_ERROR("Timeout waiting for read data.\n"); 185 186 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); 187 } 188 189 /* XXX: fix for reads and writes */ 190 return 4 + packet.payload_length; 191 } 192 193 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 194 struct mipi_dsi_device *dsi) 195 { 196 return 0; 197 } 198 199 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 200 struct mipi_dsi_device *dsi) 201 { 202 return 0; 203 } 204 205 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 206 .attach = intel_dsi_host_attach, 207 .detach = intel_dsi_host_detach, 208 .transfer = intel_dsi_host_transfer, 209 }; 210 211 /* 212 * send a video mode command 213 * 214 * XXX: commands with data in MIPI_DPI_DATA? 215 */ 216 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 217 enum port port) 218 { 219 struct drm_encoder *encoder = &intel_dsi->base.base; 220 struct drm_device *dev = encoder->dev; 221 struct drm_i915_private *dev_priv = to_i915(dev); 222 u32 mask; 223 224 /* XXX: pipe, hs */ 225 if (hs) 226 cmd &= ~DPI_LP_MODE; 227 else 228 cmd |= DPI_LP_MODE; 229 230 /* clear bit */ 231 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 232 233 /* XXX: old code skips write if control unchanged */ 234 if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) 235 DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd); 236 237 I915_WRITE(MIPI_DPI_CONTROL(port), cmd); 238 239 mask = SPL_PKT_SENT_INTERRUPT; 240 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) 241 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); 242 243 return 0; 244 } 245 246 static void band_gap_reset(struct drm_i915_private *dev_priv) 247 { 248 vlv_flisdsi_get(dev_priv); 249 250 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 251 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 252 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 253 udelay(150); 254 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 255 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 256 257 vlv_flisdsi_put(dev_priv); 258 } 259 260 static int intel_dsi_compute_config(struct intel_encoder *encoder, 261 struct intel_crtc_state *pipe_config, 262 struct drm_connector_state *conn_state) 263 { 264 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 265 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 266 base); 267 struct intel_connector *intel_connector = intel_dsi->attached_connector; 268 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 269 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 270 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 271 int ret; 272 273 DRM_DEBUG_KMS("\n"); 274 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 275 276 if (fixed_mode) { 277 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 278 279 if (HAS_GMCH(dev_priv)) 280 intel_gmch_panel_fitting(crtc, pipe_config, 281 conn_state->scaling_mode); 282 else 283 intel_pch_panel_fitting(crtc, pipe_config, 284 conn_state->scaling_mode); 285 } 286 287 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 288 return -EINVAL; 289 290 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 291 adjusted_mode->flags = 0; 292 293 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 294 pipe_config->pipe_bpp = 24; 295 else 296 pipe_config->pipe_bpp = 18; 297 298 if (IS_GEN9_LP(dev_priv)) { 299 /* Enable Frame time stamp based scanline reporting */ 300 adjusted_mode->private_flags |= 301 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 302 303 /* Dual link goes to DSI transcoder A. */ 304 if (intel_dsi->ports == BIT(PORT_C)) 305 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 306 else 307 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 308 309 ret = bxt_dsi_pll_compute(encoder, pipe_config); 310 if (ret) 311 return -EINVAL; 312 } else { 313 ret = vlv_dsi_pll_compute(encoder, pipe_config); 314 if (ret) 315 return -EINVAL; 316 } 317 318 pipe_config->clock_set = true; 319 320 return 0; 321 } 322 323 static bool glk_dsi_enable_io(struct intel_encoder *encoder) 324 { 325 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 326 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 327 enum port port; 328 u32 tmp; 329 bool cold_boot = false; 330 331 /* Set the MIPI mode 332 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 333 * Power ON MIPI IO first and then write into IO reset and LP wake bits 334 */ 335 for_each_dsi_port(port, intel_dsi->ports) { 336 tmp = I915_READ(MIPI_CTRL(port)); 337 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); 338 } 339 340 /* Put the IO into reset */ 341 tmp = I915_READ(MIPI_CTRL(PORT_A)); 342 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 343 I915_WRITE(MIPI_CTRL(PORT_A), tmp); 344 345 /* Program LP Wake */ 346 for_each_dsi_port(port, intel_dsi->ports) { 347 tmp = I915_READ(MIPI_CTRL(port)); 348 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) 349 tmp &= ~GLK_LP_WAKE; 350 else 351 tmp |= GLK_LP_WAKE; 352 I915_WRITE(MIPI_CTRL(port), tmp); 353 } 354 355 /* Wait for Pwr ACK */ 356 for_each_dsi_port(port, intel_dsi->ports) { 357 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 358 GLK_MIPIIO_PORT_POWERED, 20)) 359 DRM_ERROR("MIPIO port is powergated\n"); 360 } 361 362 /* Check for cold boot scenario */ 363 for_each_dsi_port(port, intel_dsi->ports) { 364 cold_boot |= 365 !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY); 366 } 367 368 return cold_boot; 369 } 370 371 static void glk_dsi_device_ready(struct intel_encoder *encoder) 372 { 373 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 374 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 375 enum port port; 376 u32 val; 377 378 /* Wait for MIPI PHY status bit to set */ 379 for_each_dsi_port(port, intel_dsi->ports) { 380 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 381 GLK_PHY_STATUS_PORT_READY, 20)) 382 DRM_ERROR("PHY is not ON\n"); 383 } 384 385 /* Get IO out of reset */ 386 val = I915_READ(MIPI_CTRL(PORT_A)); 387 I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED); 388 389 /* Get IO out of Low power state*/ 390 for_each_dsi_port(port, intel_dsi->ports) { 391 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { 392 val = I915_READ(MIPI_DEVICE_READY(port)); 393 val &= ~ULPS_STATE_MASK; 394 val |= DEVICE_READY; 395 I915_WRITE(MIPI_DEVICE_READY(port), val); 396 usleep_range(10, 15); 397 } else { 398 /* Enter ULPS */ 399 val = I915_READ(MIPI_DEVICE_READY(port)); 400 val &= ~ULPS_STATE_MASK; 401 val |= (ULPS_STATE_ENTER | DEVICE_READY); 402 I915_WRITE(MIPI_DEVICE_READY(port), val); 403 404 /* Wait for ULPS active */ 405 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 406 GLK_ULPS_NOT_ACTIVE, 20)) 407 DRM_ERROR("ULPS not active\n"); 408 409 /* Exit ULPS */ 410 val = I915_READ(MIPI_DEVICE_READY(port)); 411 val &= ~ULPS_STATE_MASK; 412 val |= (ULPS_STATE_EXIT | DEVICE_READY); 413 I915_WRITE(MIPI_DEVICE_READY(port), val); 414 415 /* Enter Normal Mode */ 416 val = I915_READ(MIPI_DEVICE_READY(port)); 417 val &= ~ULPS_STATE_MASK; 418 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 419 I915_WRITE(MIPI_DEVICE_READY(port), val); 420 421 val = I915_READ(MIPI_CTRL(port)); 422 val &= ~GLK_LP_WAKE; 423 I915_WRITE(MIPI_CTRL(port), val); 424 } 425 } 426 427 /* Wait for Stop state */ 428 for_each_dsi_port(port, intel_dsi->ports) { 429 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 430 GLK_DATA_LANE_STOP_STATE, 20)) 431 DRM_ERROR("Date lane not in STOP state\n"); 432 } 433 434 /* Wait for AFE LATCH */ 435 for_each_dsi_port(port, intel_dsi->ports) { 436 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), 437 AFE_LATCHOUT, 20)) 438 DRM_ERROR("D-PHY not entering LP-11 state\n"); 439 } 440 } 441 442 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 443 { 444 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 445 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 446 enum port port; 447 u32 val; 448 449 DRM_DEBUG_KMS("\n"); 450 451 /* Enable MIPI PHY transparent latch */ 452 for_each_dsi_port(port, intel_dsi->ports) { 453 val = I915_READ(BXT_MIPI_PORT_CTRL(port)); 454 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); 455 usleep_range(2000, 2500); 456 } 457 458 /* Clear ULPS and set device ready */ 459 for_each_dsi_port(port, intel_dsi->ports) { 460 val = I915_READ(MIPI_DEVICE_READY(port)); 461 val &= ~ULPS_STATE_MASK; 462 I915_WRITE(MIPI_DEVICE_READY(port), val); 463 usleep_range(2000, 2500); 464 val |= DEVICE_READY; 465 I915_WRITE(MIPI_DEVICE_READY(port), val); 466 } 467 } 468 469 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 470 { 471 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 472 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 473 enum port port; 474 u32 val; 475 476 DRM_DEBUG_KMS("\n"); 477 478 vlv_flisdsi_get(dev_priv); 479 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 480 * needed everytime after power gate */ 481 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 482 vlv_flisdsi_put(dev_priv); 483 484 /* bandgap reset is needed after everytime we do power gate */ 485 band_gap_reset(dev_priv); 486 487 for_each_dsi_port(port, intel_dsi->ports) { 488 489 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); 490 usleep_range(2500, 3000); 491 492 /* Enable MIPI PHY transparent latch 493 * Common bit for both MIPI Port A & MIPI Port C 494 * No similar bit in MIPI Port C reg 495 */ 496 val = I915_READ(MIPI_PORT_CTRL(PORT_A)); 497 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); 498 usleep_range(1000, 1500); 499 500 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); 501 usleep_range(2500, 3000); 502 503 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); 504 usleep_range(2500, 3000); 505 } 506 } 507 508 static void intel_dsi_device_ready(struct intel_encoder *encoder) 509 { 510 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 511 512 if (IS_GEMINILAKE(dev_priv)) 513 glk_dsi_device_ready(encoder); 514 else if (IS_GEN9_LP(dev_priv)) 515 bxt_dsi_device_ready(encoder); 516 else 517 vlv_dsi_device_ready(encoder); 518 } 519 520 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 521 { 522 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 523 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 524 enum port port; 525 u32 val; 526 527 /* Enter ULPS */ 528 for_each_dsi_port(port, intel_dsi->ports) { 529 val = I915_READ(MIPI_DEVICE_READY(port)); 530 val &= ~ULPS_STATE_MASK; 531 val |= (ULPS_STATE_ENTER | DEVICE_READY); 532 I915_WRITE(MIPI_DEVICE_READY(port), val); 533 } 534 535 /* Wait for MIPI PHY status bit to unset */ 536 for_each_dsi_port(port, intel_dsi->ports) { 537 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 538 GLK_PHY_STATUS_PORT_READY, 20)) 539 DRM_ERROR("PHY is not turning OFF\n"); 540 } 541 542 /* Wait for Pwr ACK bit to unset */ 543 for_each_dsi_port(port, intel_dsi->ports) { 544 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 545 GLK_MIPIIO_PORT_POWERED, 20)) 546 DRM_ERROR("MIPI IO Port is not powergated\n"); 547 } 548 } 549 550 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 551 { 552 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 553 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 554 enum port port; 555 u32 tmp; 556 557 /* Put the IO into reset */ 558 tmp = I915_READ(MIPI_CTRL(PORT_A)); 559 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 560 I915_WRITE(MIPI_CTRL(PORT_A), tmp); 561 562 /* Wait for MIPI PHY status bit to unset */ 563 for_each_dsi_port(port, intel_dsi->ports) { 564 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 565 GLK_PHY_STATUS_PORT_READY, 20)) 566 DRM_ERROR("PHY is not turning OFF\n"); 567 } 568 569 /* Clear MIPI mode */ 570 for_each_dsi_port(port, intel_dsi->ports) { 571 tmp = I915_READ(MIPI_CTRL(port)); 572 tmp &= ~GLK_MIPIIO_ENABLE; 573 I915_WRITE(MIPI_CTRL(port), tmp); 574 } 575 } 576 577 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 578 { 579 glk_dsi_enter_low_power_mode(encoder); 580 glk_dsi_disable_mipi_io(encoder); 581 } 582 583 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 584 { 585 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 586 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 587 enum port port; 588 589 DRM_DEBUG_KMS("\n"); 590 for_each_dsi_port(port, intel_dsi->ports) { 591 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 592 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 593 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); 594 u32 val; 595 596 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 597 ULPS_STATE_ENTER); 598 usleep_range(2000, 2500); 599 600 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 601 ULPS_STATE_EXIT); 602 usleep_range(2000, 2500); 603 604 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 605 ULPS_STATE_ENTER); 606 usleep_range(2000, 2500); 607 608 /* 609 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 610 * Port A only. MIPI Port C has no similar bit for checking. 611 */ 612 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && 613 intel_de_wait_for_clear(dev_priv, port_ctrl, 614 AFE_LATCHOUT, 30)) 615 DRM_ERROR("DSI LP not going Low\n"); 616 617 /* Disable MIPI PHY transparent latch */ 618 val = I915_READ(port_ctrl); 619 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); 620 usleep_range(1000, 1500); 621 622 I915_WRITE(MIPI_DEVICE_READY(port), 0x00); 623 usleep_range(2000, 2500); 624 } 625 } 626 627 static void intel_dsi_port_enable(struct intel_encoder *encoder, 628 const struct intel_crtc_state *crtc_state) 629 { 630 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 631 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 632 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 633 enum port port; 634 635 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 636 u32 temp; 637 if (IS_GEN9_LP(dev_priv)) { 638 for_each_dsi_port(port, intel_dsi->ports) { 639 temp = I915_READ(MIPI_CTRL(port)); 640 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | 641 intel_dsi->pixel_overlap << 642 BXT_PIXEL_OVERLAP_CNT_SHIFT; 643 I915_WRITE(MIPI_CTRL(port), temp); 644 } 645 } else { 646 temp = I915_READ(VLV_CHICKEN_3); 647 temp &= ~PIXEL_OVERLAP_CNT_MASK | 648 intel_dsi->pixel_overlap << 649 PIXEL_OVERLAP_CNT_SHIFT; 650 I915_WRITE(VLV_CHICKEN_3, temp); 651 } 652 } 653 654 for_each_dsi_port(port, intel_dsi->ports) { 655 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 656 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 657 u32 temp; 658 659 temp = I915_READ(port_ctrl); 660 661 temp &= ~LANE_CONFIGURATION_MASK; 662 temp &= ~DUAL_LINK_MODE_MASK; 663 664 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 665 temp |= (intel_dsi->dual_link - 1) 666 << DUAL_LINK_MODE_SHIFT; 667 if (IS_BROXTON(dev_priv)) 668 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 669 else 670 temp |= crtc->pipe ? 671 LANE_CONFIGURATION_DUAL_LINK_B : 672 LANE_CONFIGURATION_DUAL_LINK_A; 673 } 674 675 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) 676 temp |= DITHERING_ENABLE; 677 678 /* assert ip_tg_enable signal */ 679 I915_WRITE(port_ctrl, temp | DPI_ENABLE); 680 POSTING_READ(port_ctrl); 681 } 682 } 683 684 static void intel_dsi_port_disable(struct intel_encoder *encoder) 685 { 686 struct drm_device *dev = encoder->base.dev; 687 struct drm_i915_private *dev_priv = to_i915(dev); 688 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 689 enum port port; 690 691 for_each_dsi_port(port, intel_dsi->ports) { 692 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 693 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 694 u32 temp; 695 696 /* de-assert ip_tg_enable signal */ 697 temp = I915_READ(port_ctrl); 698 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); 699 POSTING_READ(port_ctrl); 700 } 701 } 702 703 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 704 const struct intel_crtc_state *pipe_config); 705 static void intel_dsi_unprepare(struct intel_encoder *encoder); 706 707 /* 708 * Panel enable/disable sequences from the VBT spec. 709 * 710 * Note the spec has AssertReset / DeassertReset swapped from their 711 * usual naming. We use the normal names to avoid confusion (so below 712 * they are swapped compared to the spec). 713 * 714 * Steps starting with MIPI refer to VBT sequences, note that for v2 715 * VBTs several steps which have a VBT in v2 are expected to be handled 716 * directly by the driver, by directly driving gpios for example. 717 * 718 * v2 video mode seq v3 video mode seq command mode seq 719 * - power on - MIPIPanelPowerOn - power on 720 * - wait t1+t2 - wait t1+t2 721 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 722 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 723 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 724 * - MIPITearOn 725 * - MIPIDisplayOn 726 * - turn on DPI - turn on DPI - set pipe to dsr mode 727 * - MIPIDisplayOn - MIPIDisplayOn 728 * - wait t5 - wait t5 729 * - backlight on - MIPIBacklightOn - backlight on 730 * ... ... ... issue mem cmds ... 731 * - backlight off - MIPIBacklightOff - backlight off 732 * - wait t6 - wait t6 733 * - MIPIDisplayOff 734 * - turn off DPI - turn off DPI - disable pipe dsr mode 735 * - MIPITearOff 736 * - MIPIDisplayOff - MIPIDisplayOff 737 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 738 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 739 * - wait t3 - wait t3 740 * - power off - MIPIPanelPowerOff - power off 741 * - wait t4 - wait t4 742 */ 743 744 /* 745 * DSI port enable has to be done before pipe and plane enable, so we do it in 746 * the pre_enable hook instead of the enable hook. 747 */ 748 static void intel_dsi_pre_enable(struct intel_encoder *encoder, 749 const struct intel_crtc_state *pipe_config, 750 const struct drm_connector_state *conn_state) 751 { 752 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 753 struct drm_crtc *crtc = pipe_config->uapi.crtc; 754 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 756 enum pipe pipe = intel_crtc->pipe; 757 enum port port; 758 u32 val; 759 bool glk_cold_boot = false; 760 761 DRM_DEBUG_KMS("\n"); 762 763 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 764 765 /* 766 * The BIOS may leave the PLL in a wonky state where it doesn't 767 * lock. It needs to be fully powered down to fix it. 768 */ 769 if (IS_GEN9_LP(dev_priv)) { 770 bxt_dsi_pll_disable(encoder); 771 bxt_dsi_pll_enable(encoder, pipe_config); 772 } else { 773 vlv_dsi_pll_disable(encoder); 774 vlv_dsi_pll_enable(encoder, pipe_config); 775 } 776 777 if (IS_BROXTON(dev_priv)) { 778 /* Add MIPI IO reset programming for modeset */ 779 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 780 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 781 val | MIPIO_RST_CTRL); 782 783 /* Power up DSI regulator */ 784 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 785 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0); 786 } 787 788 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 789 u32 val; 790 791 /* Disable DPOunit clock gating, can stall pipe */ 792 val = I915_READ(DSPCLK_GATE_D); 793 val |= DPOUNIT_CLOCK_GATE_DISABLE; 794 I915_WRITE(DSPCLK_GATE_D, val); 795 } 796 797 if (!IS_GEMINILAKE(dev_priv)) 798 intel_dsi_prepare(encoder, pipe_config); 799 800 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 801 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 802 803 /* Deassert reset */ 804 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 805 806 if (IS_GEMINILAKE(dev_priv)) { 807 glk_cold_boot = glk_dsi_enable_io(encoder); 808 809 /* Prepare port in cold boot(s3/s4) scenario */ 810 if (glk_cold_boot) 811 intel_dsi_prepare(encoder, pipe_config); 812 } 813 814 /* Put device in ready state (LP-11) */ 815 intel_dsi_device_ready(encoder); 816 817 /* Prepare port in normal boot scenario */ 818 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) 819 intel_dsi_prepare(encoder, pipe_config); 820 821 /* Send initialization commands in LP mode */ 822 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 823 824 /* Enable port in pre-enable phase itself because as per hw team 825 * recommendation, port should be enabled befor plane & pipe */ 826 if (is_cmd_mode(intel_dsi)) { 827 for_each_dsi_port(port, intel_dsi->ports) 828 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 829 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 830 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 831 } else { 832 msleep(20); /* XXX */ 833 for_each_dsi_port(port, intel_dsi->ports) 834 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 835 intel_dsi_msleep(intel_dsi, 100); 836 837 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 838 839 intel_dsi_port_enable(encoder, pipe_config); 840 } 841 842 intel_panel_enable_backlight(pipe_config, conn_state); 843 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 844 } 845 846 /* 847 * DSI port disable has to be done after pipe and plane disable, so we do it in 848 * the post_disable hook. 849 */ 850 static void intel_dsi_disable(struct intel_encoder *encoder, 851 const struct intel_crtc_state *old_crtc_state, 852 const struct drm_connector_state *old_conn_state) 853 { 854 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 855 enum port port; 856 857 DRM_DEBUG_KMS("\n"); 858 859 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 860 intel_panel_disable_backlight(old_conn_state); 861 862 /* 863 * According to the spec we should send SHUTDOWN before 864 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 865 * has shown that the v3 sequence works for v2 VBTs too 866 */ 867 if (is_vid_mode(intel_dsi)) { 868 /* Send Shutdown command to the panel in LP mode */ 869 for_each_dsi_port(port, intel_dsi->ports) 870 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 871 msleep(10); 872 } 873 } 874 875 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 876 { 877 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 878 879 if (IS_GEMINILAKE(dev_priv)) 880 glk_dsi_clear_device_ready(encoder); 881 else 882 vlv_dsi_clear_device_ready(encoder); 883 } 884 885 static void intel_dsi_post_disable(struct intel_encoder *encoder, 886 const struct intel_crtc_state *old_crtc_state, 887 const struct drm_connector_state *old_conn_state) 888 { 889 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 890 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 891 enum port port; 892 u32 val; 893 894 DRM_DEBUG_KMS("\n"); 895 896 if (IS_GEN9_LP(dev_priv)) { 897 intel_crtc_vblank_off(old_crtc_state); 898 899 skl_scaler_disable(old_crtc_state); 900 } 901 902 if (is_vid_mode(intel_dsi)) { 903 for_each_dsi_port(port, intel_dsi->ports) 904 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 905 906 intel_dsi_port_disable(encoder); 907 usleep_range(2000, 5000); 908 } 909 910 intel_dsi_unprepare(encoder); 911 912 /* 913 * if disable packets are sent before sending shutdown packet then in 914 * some next enable sequence send turn on packet error is observed 915 */ 916 if (is_cmd_mode(intel_dsi)) 917 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 918 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 919 920 /* Transition to LP-00 */ 921 intel_dsi_clear_device_ready(encoder); 922 923 if (IS_BROXTON(dev_priv)) { 924 /* Power down DSI regulator to save power */ 925 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 926 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT); 927 928 /* Add MIPI IO reset programming for modeset */ 929 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 930 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 931 val & ~MIPIO_RST_CTRL); 932 } 933 934 if (IS_GEN9_LP(dev_priv)) { 935 bxt_dsi_pll_disable(encoder); 936 } else { 937 u32 val; 938 939 vlv_dsi_pll_disable(encoder); 940 941 val = I915_READ(DSPCLK_GATE_D); 942 val &= ~DPOUNIT_CLOCK_GATE_DISABLE; 943 I915_WRITE(DSPCLK_GATE_D, val); 944 } 945 946 /* Assert reset */ 947 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 948 949 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); 950 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 951 952 /* 953 * FIXME As we do with eDP, just make a note of the time here 954 * and perform the wait before the next panel power on. 955 */ 956 intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); 957 } 958 959 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 960 enum pipe *pipe) 961 { 962 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 963 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 964 intel_wakeref_t wakeref; 965 enum port port; 966 bool active = false; 967 968 DRM_DEBUG_KMS("\n"); 969 970 wakeref = intel_display_power_get_if_enabled(dev_priv, 971 encoder->power_domain); 972 if (!wakeref) 973 return false; 974 975 /* 976 * On Broxton the PLL needs to be enabled with a valid divider 977 * configuration, otherwise accessing DSI registers will hang the 978 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 979 */ 980 if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) 981 goto out_put_power; 982 983 /* XXX: this only works for one DSI output */ 984 for_each_dsi_port(port, intel_dsi->ports) { 985 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? 986 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 987 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; 988 989 /* 990 * Due to some hardware limitations on VLV/CHV, the DPI enable 991 * bit in port C control register does not get set. As a 992 * workaround, check pipe B conf instead. 993 */ 994 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 995 port == PORT_C) 996 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 997 998 /* Try command mode if video mode not enabled */ 999 if (!enabled) { 1000 u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); 1001 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 1002 } 1003 1004 if (!enabled) 1005 continue; 1006 1007 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) 1008 continue; 1009 1010 if (IS_GEN9_LP(dev_priv)) { 1011 u32 tmp = I915_READ(MIPI_CTRL(port)); 1012 tmp &= BXT_PIPE_SELECT_MASK; 1013 tmp >>= BXT_PIPE_SELECT_SHIFT; 1014 1015 if (WARN_ON(tmp > PIPE_C)) 1016 continue; 1017 1018 *pipe = tmp; 1019 } else { 1020 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 1021 } 1022 1023 active = true; 1024 break; 1025 } 1026 1027 out_put_power: 1028 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1029 1030 return active; 1031 } 1032 1033 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1034 struct intel_crtc_state *pipe_config) 1035 { 1036 struct drm_device *dev = encoder->base.dev; 1037 struct drm_i915_private *dev_priv = to_i915(dev); 1038 struct drm_display_mode *adjusted_mode = 1039 &pipe_config->hw.adjusted_mode; 1040 struct drm_display_mode *adjusted_mode_sw; 1041 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1042 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1043 unsigned int lane_count = intel_dsi->lane_count; 1044 unsigned int bpp, fmt; 1045 enum port port; 1046 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1047 u16 hfp_sw, hsync_sw, hbp_sw; 1048 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1049 crtc_hblank_start_sw, crtc_hblank_end_sw; 1050 1051 /* FIXME: hw readout should not depend on SW state */ 1052 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; 1053 1054 /* 1055 * Atleast one port is active as encoder->get_config called only if 1056 * encoder->get_hw_state() returns true. 1057 */ 1058 for_each_dsi_port(port, intel_dsi->ports) { 1059 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1060 break; 1061 } 1062 1063 fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; 1064 bpp = mipi_dsi_pixel_format_to_bpp( 1065 pixel_format_from_register_bits(fmt)); 1066 1067 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1068 1069 /* Enable Frame time stamo based scanline reporting */ 1070 adjusted_mode->private_flags |= 1071 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 1072 1073 /* In terms of pixels */ 1074 adjusted_mode->crtc_hdisplay = 1075 I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); 1076 adjusted_mode->crtc_vdisplay = 1077 I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); 1078 adjusted_mode->crtc_vtotal = 1079 I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); 1080 1081 hactive = adjusted_mode->crtc_hdisplay; 1082 hfp = I915_READ(MIPI_HFP_COUNT(port)); 1083 1084 /* 1085 * Meaningful for video mode non-burst sync pulse mode only, 1086 * can be zero for non-burst sync events and burst modes 1087 */ 1088 hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); 1089 hbp = I915_READ(MIPI_HBP_COUNT(port)); 1090 1091 /* harizontal values are in terms of high speed byte clock */ 1092 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1093 intel_dsi->burst_mode_ratio); 1094 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1095 intel_dsi->burst_mode_ratio); 1096 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1097 intel_dsi->burst_mode_ratio); 1098 1099 if (intel_dsi->dual_link) { 1100 hfp *= 2; 1101 hsync *= 2; 1102 hbp *= 2; 1103 } 1104 1105 /* vertical values are in terms of lines */ 1106 vfp = I915_READ(MIPI_VFP_COUNT(port)); 1107 vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); 1108 vbp = I915_READ(MIPI_VBP_COUNT(port)); 1109 1110 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1111 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1112 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1113 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1114 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1115 1116 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1117 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1118 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1119 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1120 1121 /* 1122 * In BXT DSI there is no regs programmed with few horizontal timings 1123 * in Pixels but txbyteclkhs.. So retrieval process adds some 1124 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1125 * Actually here for the given adjusted_mode, we are calculating the 1126 * value programmed to the port and then back to the horizontal timing 1127 * param in pixels. This is the expected value, including roundup errors 1128 * And if that is same as retrieved value from port, then 1129 * (HW state) adjusted_mode's horizontal timings are corrected to 1130 * match with SW state to nullify the errors. 1131 */ 1132 /* Calculating the value programmed to the Port register */ 1133 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1134 adjusted_mode_sw->crtc_hdisplay; 1135 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1136 adjusted_mode_sw->crtc_hsync_start; 1137 hbp_sw = adjusted_mode_sw->crtc_htotal - 1138 adjusted_mode_sw->crtc_hsync_end; 1139 1140 if (intel_dsi->dual_link) { 1141 hfp_sw /= 2; 1142 hsync_sw /= 2; 1143 hbp_sw /= 2; 1144 } 1145 1146 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1147 intel_dsi->burst_mode_ratio); 1148 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1149 intel_dsi->burst_mode_ratio); 1150 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1151 intel_dsi->burst_mode_ratio); 1152 1153 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1154 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1155 intel_dsi->burst_mode_ratio); 1156 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1157 intel_dsi->burst_mode_ratio); 1158 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1159 intel_dsi->burst_mode_ratio); 1160 1161 if (intel_dsi->dual_link) { 1162 hfp_sw *= 2; 1163 hsync_sw *= 2; 1164 hbp_sw *= 2; 1165 } 1166 1167 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1168 hsync_sw + hbp_sw; 1169 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1170 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1171 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1172 crtc_hblank_end_sw = crtc_htotal_sw; 1173 1174 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1175 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1176 1177 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1178 adjusted_mode->crtc_hsync_start = 1179 adjusted_mode_sw->crtc_hsync_start; 1180 1181 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1182 adjusted_mode->crtc_hsync_end = 1183 adjusted_mode_sw->crtc_hsync_end; 1184 1185 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1186 adjusted_mode->crtc_hblank_start = 1187 adjusted_mode_sw->crtc_hblank_start; 1188 1189 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1190 adjusted_mode->crtc_hblank_end = 1191 adjusted_mode_sw->crtc_hblank_end; 1192 } 1193 1194 static void intel_dsi_get_config(struct intel_encoder *encoder, 1195 struct intel_crtc_state *pipe_config) 1196 { 1197 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1198 u32 pclk; 1199 DRM_DEBUG_KMS("\n"); 1200 1201 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1202 1203 if (IS_GEN9_LP(dev_priv)) { 1204 bxt_dsi_get_pipe_config(encoder, pipe_config); 1205 pclk = bxt_dsi_get_pclk(encoder, pipe_config); 1206 } else { 1207 pclk = vlv_dsi_get_pclk(encoder, pipe_config); 1208 } 1209 1210 if (pclk) { 1211 pipe_config->hw.adjusted_mode.crtc_clock = pclk; 1212 pipe_config->port_clock = pclk; 1213 } 1214 } 1215 1216 /* return txclkesc cycles in terms of divider and duration in us */ 1217 static u16 txclkesc(u32 divider, unsigned int us) 1218 { 1219 switch (divider) { 1220 case ESCAPE_CLOCK_DIVIDER_1: 1221 default: 1222 return 20 * us; 1223 case ESCAPE_CLOCK_DIVIDER_2: 1224 return 10 * us; 1225 case ESCAPE_CLOCK_DIVIDER_4: 1226 return 5 * us; 1227 } 1228 } 1229 1230 static void set_dsi_timings(struct drm_encoder *encoder, 1231 const struct drm_display_mode *adjusted_mode) 1232 { 1233 struct drm_device *dev = encoder->dev; 1234 struct drm_i915_private *dev_priv = to_i915(dev); 1235 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1236 enum port port; 1237 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1238 unsigned int lane_count = intel_dsi->lane_count; 1239 1240 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1241 1242 hactive = adjusted_mode->crtc_hdisplay; 1243 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1244 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1245 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1246 1247 if (intel_dsi->dual_link) { 1248 hactive /= 2; 1249 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1250 hactive += intel_dsi->pixel_overlap; 1251 hfp /= 2; 1252 hsync /= 2; 1253 hbp /= 2; 1254 } 1255 1256 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1257 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1258 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1259 1260 /* horizontal values are in terms of high speed byte clock */ 1261 hactive = txbyteclkhs(hactive, bpp, lane_count, 1262 intel_dsi->burst_mode_ratio); 1263 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1264 hsync = txbyteclkhs(hsync, bpp, lane_count, 1265 intel_dsi->burst_mode_ratio); 1266 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1267 1268 for_each_dsi_port(port, intel_dsi->ports) { 1269 if (IS_GEN9_LP(dev_priv)) { 1270 /* 1271 * Program hdisplay and vdisplay on MIPI transcoder. 1272 * This is different from calculated hactive and 1273 * vactive, as they are calculated per channel basis, 1274 * whereas these values should be based on resolution. 1275 */ 1276 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), 1277 adjusted_mode->crtc_hdisplay); 1278 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), 1279 adjusted_mode->crtc_vdisplay); 1280 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), 1281 adjusted_mode->crtc_vtotal); 1282 } 1283 1284 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); 1285 I915_WRITE(MIPI_HFP_COUNT(port), hfp); 1286 1287 /* meaningful for video mode non-burst sync pulse mode only, 1288 * can be zero for non-burst sync events and burst modes */ 1289 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); 1290 I915_WRITE(MIPI_HBP_COUNT(port), hbp); 1291 1292 /* vertical values are in terms of lines */ 1293 I915_WRITE(MIPI_VFP_COUNT(port), vfp); 1294 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); 1295 I915_WRITE(MIPI_VBP_COUNT(port), vbp); 1296 } 1297 } 1298 1299 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1300 { 1301 switch (fmt) { 1302 case MIPI_DSI_FMT_RGB888: 1303 return VID_MODE_FORMAT_RGB888; 1304 case MIPI_DSI_FMT_RGB666: 1305 return VID_MODE_FORMAT_RGB666; 1306 case MIPI_DSI_FMT_RGB666_PACKED: 1307 return VID_MODE_FORMAT_RGB666_PACKED; 1308 case MIPI_DSI_FMT_RGB565: 1309 return VID_MODE_FORMAT_RGB565; 1310 default: 1311 MISSING_CASE(fmt); 1312 return VID_MODE_FORMAT_RGB666; 1313 } 1314 } 1315 1316 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 1317 const struct intel_crtc_state *pipe_config) 1318 { 1319 struct drm_encoder *encoder = &intel_encoder->base; 1320 struct drm_device *dev = encoder->dev; 1321 struct drm_i915_private *dev_priv = to_i915(dev); 1322 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 1323 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1324 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1325 enum port port; 1326 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1327 u32 val, tmp; 1328 u16 mode_hdisplay; 1329 1330 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); 1331 1332 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1333 1334 if (intel_dsi->dual_link) { 1335 mode_hdisplay /= 2; 1336 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1337 mode_hdisplay += intel_dsi->pixel_overlap; 1338 } 1339 1340 for_each_dsi_port(port, intel_dsi->ports) { 1341 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1342 /* 1343 * escape clock divider, 20MHz, shared for A and C. 1344 * device ready must be off when doing this! txclkesc? 1345 */ 1346 tmp = I915_READ(MIPI_CTRL(PORT_A)); 1347 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1348 I915_WRITE(MIPI_CTRL(PORT_A), tmp | 1349 ESCAPE_CLOCK_DIVIDER_1); 1350 1351 /* read request priority is per pipe */ 1352 tmp = I915_READ(MIPI_CTRL(port)); 1353 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1354 I915_WRITE(MIPI_CTRL(port), tmp | 1355 READ_REQUEST_PRIORITY_HIGH); 1356 } else if (IS_GEN9_LP(dev_priv)) { 1357 enum pipe pipe = intel_crtc->pipe; 1358 1359 tmp = I915_READ(MIPI_CTRL(port)); 1360 tmp &= ~BXT_PIPE_SELECT_MASK; 1361 1362 tmp |= BXT_PIPE_SELECT(pipe); 1363 I915_WRITE(MIPI_CTRL(port), tmp); 1364 } 1365 1366 /* XXX: why here, why like this? handling in irq handler?! */ 1367 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); 1368 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); 1369 1370 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); 1371 1372 I915_WRITE(MIPI_DPI_RESOLUTION(port), 1373 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | 1374 mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1375 } 1376 1377 set_dsi_timings(encoder, adjusted_mode); 1378 1379 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1380 if (is_cmd_mode(intel_dsi)) { 1381 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1382 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1383 } else { 1384 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1385 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1386 } 1387 1388 tmp = 0; 1389 if (intel_dsi->eotp_pkt == 0) 1390 tmp |= EOT_DISABLE; 1391 if (intel_dsi->clock_stop) 1392 tmp |= CLOCKSTOP; 1393 1394 if (IS_GEN9_LP(dev_priv)) { 1395 tmp |= BXT_DPHY_DEFEATURE_EN; 1396 if (!is_cmd_mode(intel_dsi)) 1397 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1398 } 1399 1400 for_each_dsi_port(port, intel_dsi->ports) { 1401 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); 1402 1403 /* timeouts for recovery. one frame IIUC. if counter expires, 1404 * EOT and stop state. */ 1405 1406 /* 1407 * In burst mode, value greater than one DPI line Time in byte 1408 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1409 * said value is recommended. 1410 * 1411 * In non-burst mode, Value greater than one DPI frame time in 1412 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1413 * said value is recommended. 1414 * 1415 * In DBI only mode, value greater than one DBI frame time in 1416 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1417 * said value is recommended. 1418 */ 1419 1420 if (is_vid_mode(intel_dsi) && 1421 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 1422 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), 1423 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, 1424 intel_dsi->lane_count, 1425 intel_dsi->burst_mode_ratio) + 1); 1426 } else { 1427 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), 1428 txbyteclkhs(adjusted_mode->crtc_vtotal * 1429 adjusted_mode->crtc_htotal, 1430 bpp, intel_dsi->lane_count, 1431 intel_dsi->burst_mode_ratio) + 1); 1432 } 1433 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); 1434 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), 1435 intel_dsi->turn_arnd_val); 1436 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), 1437 intel_dsi->rst_timer_val); 1438 1439 /* dphy stuff */ 1440 1441 /* in terms of low power clock */ 1442 I915_WRITE(MIPI_INIT_COUNT(port), 1443 txclkesc(intel_dsi->escape_clk_div, 100)); 1444 1445 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { 1446 /* 1447 * BXT spec says write MIPI_INIT_COUNT for 1448 * both the ports, even if only one is 1449 * getting used. So write the other port 1450 * if not in dual link mode. 1451 */ 1452 I915_WRITE(MIPI_INIT_COUNT(port == 1453 PORT_A ? PORT_C : PORT_A), 1454 intel_dsi->init_count); 1455 } 1456 1457 /* recovery disables */ 1458 I915_WRITE(MIPI_EOT_DISABLE(port), tmp); 1459 1460 /* in terms of low power clock */ 1461 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); 1462 1463 /* in terms of txbyteclkhs. actual high to low switch + 1464 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1465 * 1466 * XXX: write MIPI_STOP_STATE_STALL? 1467 */ 1468 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), 1469 intel_dsi->hs_to_lp_count); 1470 1471 /* XXX: low power clock equivalence in terms of byte clock. 1472 * the number of byte clocks occupied in one low power clock. 1473 * based on txbyteclkhs and txclkesc. 1474 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1475 * ) / 105.??? 1476 */ 1477 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); 1478 1479 if (IS_GEMINILAKE(dev_priv)) { 1480 I915_WRITE(MIPI_TLPX_TIME_COUNT(port), 1481 intel_dsi->lp_byte_clk); 1482 /* Shadow of DPHY reg */ 1483 I915_WRITE(MIPI_CLK_LANE_TIMING(port), 1484 intel_dsi->dphy_reg); 1485 } 1486 1487 /* the bw essential for transmitting 16 long packets containing 1488 * 252 bytes meant for dcs write memory command is programmed in 1489 * this register in terms of byte clocks. based on dsi transfer 1490 * rate and the number of lanes configured the time taken to 1491 * transmit 16 long packets in a dsi stream varies. */ 1492 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); 1493 1494 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), 1495 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | 1496 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1497 1498 if (is_vid_mode(intel_dsi)) 1499 /* Some panels might have resolution which is not a 1500 * multiple of 64 like 1366 x 768. Enable RANDOM 1501 * resolution support for such panels by default */ 1502 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), 1503 intel_dsi->video_frmt_cfg_bits | 1504 intel_dsi->video_mode_format | 1505 IP_TG_CONFIG | 1506 RANDOM_DPI_DISPLAY_RESOLUTION); 1507 } 1508 } 1509 1510 static void intel_dsi_unprepare(struct intel_encoder *encoder) 1511 { 1512 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1513 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1514 enum port port; 1515 u32 val; 1516 1517 if (IS_GEMINILAKE(dev_priv)) 1518 return; 1519 1520 for_each_dsi_port(port, intel_dsi->ports) { 1521 /* Panel commands can be sent when clock is in LP11 */ 1522 I915_WRITE(MIPI_DEVICE_READY(port), 0x0); 1523 1524 if (IS_GEN9_LP(dev_priv)) 1525 bxt_dsi_reset_clocks(encoder, port); 1526 else 1527 vlv_dsi_reset_clocks(encoder, port); 1528 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); 1529 1530 val = I915_READ(MIPI_DSI_FUNC_PRG(port)); 1531 val &= ~VID_MODE_FORMAT_MASK; 1532 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); 1533 1534 I915_WRITE(MIPI_DEVICE_READY(port), 0x1); 1535 } 1536 } 1537 1538 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) 1539 { 1540 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1541 1542 intel_dsi_vbt_gpio_cleanup(intel_dsi); 1543 intel_encoder_destroy(encoder); 1544 } 1545 1546 static const struct drm_encoder_funcs intel_dsi_funcs = { 1547 .destroy = intel_dsi_encoder_destroy, 1548 }; 1549 1550 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1551 .get_modes = intel_dsi_get_modes, 1552 .mode_valid = intel_dsi_mode_valid, 1553 .atomic_check = intel_digital_connector_atomic_check, 1554 }; 1555 1556 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1557 .late_register = intel_connector_register, 1558 .early_unregister = intel_connector_unregister, 1559 .destroy = intel_connector_destroy, 1560 .fill_modes = drm_helper_probe_single_connector_modes, 1561 .atomic_get_property = intel_digital_connector_atomic_get_property, 1562 .atomic_set_property = intel_digital_connector_atomic_set_property, 1563 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1564 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1565 }; 1566 1567 static enum drm_panel_orientation 1568 vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector) 1569 { 1570 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1571 struct intel_encoder *encoder = connector->encoder; 1572 enum intel_display_power_domain power_domain; 1573 enum drm_panel_orientation orientation; 1574 struct intel_plane *plane; 1575 struct intel_crtc *crtc; 1576 intel_wakeref_t wakeref; 1577 enum pipe pipe; 1578 u32 val; 1579 1580 if (!encoder->get_hw_state(encoder, &pipe)) 1581 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1582 1583 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1584 plane = to_intel_plane(crtc->base.primary); 1585 1586 power_domain = POWER_DOMAIN_PIPE(pipe); 1587 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1588 if (!wakeref) 1589 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1590 1591 val = I915_READ(DSPCNTR(plane->i9xx_plane)); 1592 1593 if (!(val & DISPLAY_PLANE_ENABLE)) 1594 orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1595 else if (val & DISPPLANE_ROTATE_180) 1596 orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; 1597 else 1598 orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; 1599 1600 intel_display_power_put(dev_priv, power_domain, wakeref); 1601 1602 return orientation; 1603 } 1604 1605 static enum drm_panel_orientation 1606 vlv_dsi_get_panel_orientation(struct intel_connector *connector) 1607 { 1608 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1609 enum drm_panel_orientation orientation; 1610 1611 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1612 orientation = vlv_dsi_get_hw_panel_orientation(connector); 1613 if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN) 1614 return orientation; 1615 } 1616 1617 return intel_dsi_get_panel_orientation(connector); 1618 } 1619 1620 static void vlv_dsi_add_properties(struct intel_connector *connector) 1621 { 1622 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1623 1624 if (connector->panel.fixed_mode) { 1625 u32 allowed_scalers; 1626 1627 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); 1628 if (!HAS_GMCH(dev_priv)) 1629 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 1630 1631 drm_connector_attach_scaling_mode_property(&connector->base, 1632 allowed_scalers); 1633 1634 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1635 1636 connector->base.display_info.panel_orientation = 1637 vlv_dsi_get_panel_orientation(connector); 1638 drm_connector_init_panel_orientation_property( 1639 &connector->base, 1640 connector->panel.fixed_mode->hdisplay, 1641 connector->panel.fixed_mode->vdisplay); 1642 } 1643 } 1644 1645 #define NS_KHZ_RATIO 1000000 1646 1647 #define PREPARE_CNT_MAX 0x3F 1648 #define EXIT_ZERO_CNT_MAX 0x3F 1649 #define CLK_ZERO_CNT_MAX 0xFF 1650 #define TRAIL_CNT_MAX 0x1F 1651 1652 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1653 { 1654 struct drm_device *dev = intel_dsi->base.base.dev; 1655 struct drm_i915_private *dev_priv = to_i915(dev); 1656 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1657 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1658 u32 ui_num, ui_den; 1659 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1660 u32 ths_prepare_ns, tclk_trail_ns; 1661 u32 tclk_prepare_clkzero, ths_prepare_hszero; 1662 u32 lp_to_hs_switch, hs_to_lp_switch; 1663 u32 mul; 1664 1665 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1666 1667 switch (intel_dsi->lane_count) { 1668 case 1: 1669 case 2: 1670 extra_byte_count = 2; 1671 break; 1672 case 3: 1673 extra_byte_count = 4; 1674 break; 1675 case 4: 1676 default: 1677 extra_byte_count = 3; 1678 break; 1679 } 1680 1681 /* in Kbps */ 1682 ui_num = NS_KHZ_RATIO; 1683 ui_den = intel_dsi_bitrate(intel_dsi); 1684 1685 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; 1686 ths_prepare_hszero = mipi_config->ths_prepare_hszero; 1687 1688 /* 1689 * B060 1690 * LP byte clock = TLPX/ (8UI) 1691 */ 1692 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); 1693 1694 /* DDR clock period = 2 * UI 1695 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ) 1696 * UI(nsec) = 10^6 / bitrate 1697 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate 1698 * DDR clock count = ns_value / DDR clock period 1699 * 1700 * For GEMINILAKE dphy_param_reg will be programmed in terms of 1701 * HS byte clock count for other platform in HS ddr clock count 1702 */ 1703 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; 1704 ths_prepare_ns = max(mipi_config->ths_prepare, 1705 mipi_config->tclk_prepare); 1706 1707 /* prepare count */ 1708 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); 1709 1710 if (prepare_cnt > PREPARE_CNT_MAX) { 1711 DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt); 1712 prepare_cnt = PREPARE_CNT_MAX; 1713 } 1714 1715 /* exit zero count */ 1716 exit_zero_cnt = DIV_ROUND_UP( 1717 (ths_prepare_hszero - ths_prepare_ns) * ui_den, 1718 ui_num * mul 1719 ); 1720 1721 /* 1722 * Exit zero is unified val ths_zero and ths_exit 1723 * minimum value for ths_exit = 110ns 1724 * min (exit_zero_cnt * 2) = 110/UI 1725 * exit_zero_cnt = 55/UI 1726 */ 1727 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) 1728 exit_zero_cnt += 1; 1729 1730 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { 1731 DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt); 1732 exit_zero_cnt = EXIT_ZERO_CNT_MAX; 1733 } 1734 1735 /* clk zero count */ 1736 clk_zero_cnt = DIV_ROUND_UP( 1737 (tclk_prepare_clkzero - ths_prepare_ns) 1738 * ui_den, ui_num * mul); 1739 1740 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { 1741 DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt); 1742 clk_zero_cnt = CLK_ZERO_CNT_MAX; 1743 } 1744 1745 /* trail count */ 1746 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1747 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); 1748 1749 if (trail_cnt > TRAIL_CNT_MAX) { 1750 DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt); 1751 trail_cnt = TRAIL_CNT_MAX; 1752 } 1753 1754 /* B080 */ 1755 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | 1756 clk_zero_cnt << 8 | prepare_cnt; 1757 1758 /* 1759 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * 1760 * mul + 10UI + Extra Byte Count 1761 * 1762 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count 1763 * Extra Byte Count is calculated according to number of lanes. 1764 * High Low Switch Count is the Max of LP to HS and 1765 * HS to LP switch count 1766 * 1767 */ 1768 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); 1769 1770 /* B044 */ 1771 /* FIXME: 1772 * The comment above does not match with the code */ 1773 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + 1774 exit_zero_cnt * mul + 10, 8); 1775 1776 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); 1777 1778 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); 1779 intel_dsi->hs_to_lp_count += extra_byte_count; 1780 1781 /* B088 */ 1782 /* LP -> HS for clock lanes 1783 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + 1784 * extra byte count 1785 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * 1786 * 2(in UI) + extra byte count 1787 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / 1788 * 8 + extra byte count 1789 */ 1790 intel_dsi->clk_lp_to_hs_count = 1791 DIV_ROUND_UP( 1792 4 * tlpx_ui + prepare_cnt * 2 + 1793 clk_zero_cnt * 2, 1794 8); 1795 1796 intel_dsi->clk_lp_to_hs_count += extra_byte_count; 1797 1798 /* HS->LP for Clock Lanes 1799 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + 1800 * Extra byte count 1801 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count 1802 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + 1803 * Extra byte count 1804 */ 1805 intel_dsi->clk_hs_to_lp_count = 1806 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, 1807 8); 1808 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1809 1810 intel_dsi_log_params(intel_dsi); 1811 } 1812 1813 void vlv_dsi_init(struct drm_i915_private *dev_priv) 1814 { 1815 struct drm_device *dev = &dev_priv->drm; 1816 struct intel_dsi *intel_dsi; 1817 struct intel_encoder *intel_encoder; 1818 struct drm_encoder *encoder; 1819 struct intel_connector *intel_connector; 1820 struct drm_connector *connector; 1821 struct drm_display_mode *current_mode, *fixed_mode; 1822 enum port port; 1823 enum pipe pipe; 1824 1825 DRM_DEBUG_KMS("\n"); 1826 1827 /* There is no detection method for MIPI so rely on VBT */ 1828 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1829 return; 1830 1831 if (IS_GEN9_LP(dev_priv)) 1832 dev_priv->mipi_mmio_base = BXT_MIPI_BASE; 1833 else 1834 dev_priv->mipi_mmio_base = VLV_MIPI_BASE; 1835 1836 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1837 if (!intel_dsi) 1838 return; 1839 1840 intel_connector = intel_connector_alloc(); 1841 if (!intel_connector) { 1842 kfree(intel_dsi); 1843 return; 1844 } 1845 1846 intel_encoder = &intel_dsi->base; 1847 encoder = &intel_encoder->base; 1848 intel_dsi->attached_connector = intel_connector; 1849 1850 connector = &intel_connector->base; 1851 1852 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, 1853 "DSI %c", port_name(port)); 1854 1855 intel_encoder->compute_config = intel_dsi_compute_config; 1856 intel_encoder->pre_enable = intel_dsi_pre_enable; 1857 intel_encoder->disable = intel_dsi_disable; 1858 intel_encoder->post_disable = intel_dsi_post_disable; 1859 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 1860 intel_encoder->get_config = intel_dsi_get_config; 1861 intel_encoder->update_pipe = intel_panel_update_backlight; 1862 1863 intel_connector->get_hw_state = intel_connector_get_hw_state; 1864 1865 intel_encoder->port = port; 1866 intel_encoder->type = INTEL_OUTPUT_DSI; 1867 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1868 intel_encoder->cloneable = 0; 1869 1870 /* 1871 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1872 * port C. BXT isn't limited like this. 1873 */ 1874 if (IS_GEN9_LP(dev_priv)) 1875 intel_encoder->pipe_mask = ~0; 1876 else if (port == PORT_A) 1877 intel_encoder->pipe_mask = BIT(PIPE_A); 1878 else 1879 intel_encoder->pipe_mask = BIT(PIPE_B); 1880 1881 if (dev_priv->vbt.dsi.config->dual_link) 1882 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1883 else 1884 intel_dsi->ports = BIT(port); 1885 1886 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 1887 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 1888 1889 /* Create a DSI host (and a device) for each port. */ 1890 for_each_dsi_port(port, intel_dsi->ports) { 1891 struct intel_dsi_host *host; 1892 1893 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, 1894 port); 1895 if (!host) 1896 goto err; 1897 1898 intel_dsi->dsi_hosts[port] = host; 1899 } 1900 1901 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1902 DRM_DEBUG_KMS("no device found\n"); 1903 goto err; 1904 } 1905 1906 /* Use clock read-back from current hw-state for fastboot */ 1907 current_mode = intel_encoder_current_mode(intel_encoder); 1908 if (current_mode) { 1909 DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n", 1910 intel_dsi->pclk, current_mode->clock); 1911 if (intel_fuzzy_clock_check(intel_dsi->pclk, 1912 current_mode->clock)) { 1913 DRM_DEBUG_KMS("Using GOP pclk\n"); 1914 intel_dsi->pclk = current_mode->clock; 1915 } 1916 1917 kfree(current_mode); 1918 } 1919 1920 vlv_dphy_param_init(intel_dsi); 1921 1922 intel_dsi_vbt_gpio_init(intel_dsi, 1923 intel_dsi_get_hw_state(intel_encoder, &pipe)); 1924 1925 drm_connector_init(dev, connector, &intel_dsi_connector_funcs, 1926 DRM_MODE_CONNECTOR_DSI); 1927 1928 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 1929 1930 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 1931 connector->interlace_allowed = false; 1932 connector->doublescan_allowed = false; 1933 1934 intel_connector_attach_encoder(intel_connector, intel_encoder); 1935 1936 mutex_lock(&dev->mode_config.mutex); 1937 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 1938 mutex_unlock(&dev->mode_config.mutex); 1939 1940 if (!fixed_mode) { 1941 DRM_DEBUG_KMS("no fixed mode\n"); 1942 goto err_cleanup_connector; 1943 } 1944 1945 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1946 intel_panel_setup_backlight(connector, INVALID_PIPE); 1947 1948 vlv_dsi_add_properties(intel_connector); 1949 1950 return; 1951 1952 err_cleanup_connector: 1953 drm_connector_cleanup(&intel_connector->base); 1954 err: 1955 drm_encoder_cleanup(&intel_encoder->base); 1956 kfree(intel_dsi); 1957 kfree(intel_connector); 1958 } 1959
Indexes created Sat Sep 20 22:09:52 GMT 2025