| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| hwmgr_ppt.h | 99 uint8_t lane_width; member in struct:phm_ppt_v1_pcie_record
|
| amdgpu_vega20_hwmgr.c | 3277 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; local in function:vega20_print_clock_levels
3374 lane_width = data->pcie_width_level1;
3377 lane_width = pptable->PcieLaneCount[i];
3384 (lane_width == 1) ? "x1" :
3385 (lane_width == 2) ? "x2" :
3386 (lane_width == 3) ? "x4" :
3387 (lane_width == 4) ? "x8" :
3388 (lane_width == 5) ? "x12" :
3389 (lane_width == 6) ? "x16" : "",
3392 (current_lane_width == lane_width)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_navi10_ppt.c | 772 uint32_t gen_speed, lane_width; local in function:navi10_print_clk_levels
835 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
852 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
|
| amdgpu_vega20_ppt.c | 955 uint32_t gen_speed, lane_width; local in function:vega20_print_clk_levels
1073 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1090 (lane_width == pptable->PcieLaneCount[i]) ?
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_dpm.c | 5169 u32 lane_width; local in function:si_init_smc_table
5238 lane_width = amdgpu_get_pcie_lanes(adev);
5239 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6381 u32 lane_width; local in function:si_set_pcie_lane_width_in_smc
6389 lane_width = amdgpu_get_pcie_lanes(adev);
6390 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_si_dpm.c | 4705 u32 lane_width; local in function:si_init_smc_table
4774 lane_width = radeon_get_pcie_lanes(rdev);
4775 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5921 u32 lane_width; local in function:si_set_pcie_lane_width_in_smc
5929 lane_width = radeon_get_pcie_lanes(rdev);
5930 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
|
