/src/sys/external/bsd/drm2/dist/drm/radeon/ |
cypress_dpm.h | 51 u32 mc_arb_dram_timing2; member in struct:evergreen_arb_registers
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nislands_smc.h | 283 uint32_t mc_arb_dram_timing2; member in struct:SMC_NIslands_MCArbDramTimingRegisterSet
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sislands_smc.h | 333 uint32_t mc_arb_dram_timing2; member in struct:SMC_SIslands_MCArbDramTimingRegisterSet
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radeon_ni_dpm.c | 1514 u32 mc_arb_dram_timing2; local in function:ni_copy_and_switch_arb_sets 1521 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 1526 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); 1531 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); 1536 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); 1546 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 1551 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 1556 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); [all...] |
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
sislands_smc.h | 333 uint32_t mc_arb_dram_timing2; member in struct:SMC_SIslands_MCArbDramTimingRegisterSet
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amdgpu_si_dpm.c | 3090 u32 mc_arb_dram_timing2; local in function:ni_copy_and_switch_arb_sets 3097 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 3102 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); 3107 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); 3112 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); 3122 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 3127 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 3132 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); [all...] |
si_dpm.h | 338 u32 mc_arb_dram_timing2; member in struct:evergreen_arb_registers
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/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
amdgpu_smu7_hwmgr.c | 460 uint32_t mc_arb_dram_timing2; local in function:smu7_copy_and_switch_arb_sets 467 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); 472 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); 482 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 487 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
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