1 /* $NetBSD: si_dpm.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __SI_DPM_H__ 26 #define __SI_DPM_H__ 27 28 #include "amdgpu_atombios.h" 29 #include "sislands_smc.h" 30 31 #define MC_CG_CONFIG 0x96f 32 #define MC_ARB_CG 0x9fa 33 #define CG_ARB_REQ(x) ((x) << 0) 34 #define CG_ARB_REQ_MASK (0xff << 0) 35 36 #define MC_ARB_DRAM_TIMING_1 0x9fc 37 #define MC_ARB_DRAM_TIMING_2 0x9fd 38 #define MC_ARB_DRAM_TIMING_3 0x9fe 39 #define MC_ARB_DRAM_TIMING2_1 0x9ff 40 #define MC_ARB_DRAM_TIMING2_2 0xa00 41 #define MC_ARB_DRAM_TIMING2_3 0xa01 42 43 #define MAX_NO_OF_MVDD_VALUES 2 44 #define MAX_NO_VREG_STEPS 32 45 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 46 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32 47 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 48 #define RV770_ASI_DFLT 1000 49 #define CYPRESS_HASI_DFLT 400000 50 #define PCIE_PERF_REQ_PECI_GEN1 2 51 #define PCIE_PERF_REQ_PECI_GEN2 3 52 #define PCIE_PERF_REQ_PECI_GEN3 4 53 #define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ 54 #define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ 55 56 #define SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE 16 57 58 #define RV770_SMC_TABLE_ADDRESS 0xB000 59 #define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 3 60 61 #define SMC_STROBE_RATIO 0x0F 62 #define SMC_STROBE_ENABLE 0x10 63 64 #define SMC_MC_EDC_RD_FLAG 0x01 65 #define SMC_MC_EDC_WR_FLAG 0x02 66 #define SMC_MC_RTT_ENABLE 0x04 67 #define SMC_MC_STUTTER_EN 0x08 68 69 #define RV770_SMC_VOLTAGEMASK_VDDC 0 70 #define RV770_SMC_VOLTAGEMASK_MVDD 1 71 #define RV770_SMC_VOLTAGEMASK_VDDCI 2 72 #define RV770_SMC_VOLTAGEMASK_MAX 4 73 74 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 75 #define NISLANDS_SMC_STROBE_RATIO 0x0F 76 #define NISLANDS_SMC_STROBE_ENABLE 0x10 77 78 #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01 79 #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02 80 #define NISLANDS_SMC_MC_RTT_ENABLE 0x04 81 #define NISLANDS_SMC_MC_STUTTER_EN 0x08 82 83 #define MAX_NO_VREG_STEPS 32 84 85 #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0 86 #define NISLANDS_SMC_VOLTAGEMASK_MVDD 1 87 #define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2 88 #define NISLANDS_SMC_VOLTAGEMASK_MAX 4 89 90 #define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0 91 #define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1 92 #define SISLANDS_MCREGISTERTABLE_ULV_SLOT 2 93 #define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 3 94 95 #define SISLANDS_LEAKAGE_INDEX0 0xff01 96 #define SISLANDS_MAX_LEAKAGE_COUNT 4 97 98 #define SISLANDS_MAX_HARDWARE_POWERLEVELS 5 99 #define SISLANDS_INITIAL_STATE_ARB_INDEX 0 100 #define SISLANDS_ACPI_STATE_ARB_INDEX 1 101 #define SISLANDS_ULV_STATE_ARB_INDEX 2 102 #define SISLANDS_DRIVER_STATE_ARB_INDEX 3 103 104 #define SISLANDS_DPM2_MAX_PULSE_SKIP 256 105 106 #define SISLANDS_DPM2_NEAR_TDP_DEC 10 107 #define SISLANDS_DPM2_ABOVE_SAFE_INC 5 108 #define SISLANDS_DPM2_BELOW_SAFE_INC 20 109 110 #define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80 111 112 #define SISLANDS_DPM2_MAXPS_PERCENT_H 99 113 #define SISLANDS_DPM2_MAXPS_PERCENT_M 99 114 115 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF 116 #define SISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12 117 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 118 #define SISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E 119 #define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF 120 121 #define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN 10 122 123 #define SISLANDS_VRC_DFLT 0xC000B3 124 #define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT 1687 125 #define SISLANDS_CGULVPARAMETER_DFLT 0x00040035 126 #define SISLANDS_CGULVCONTROL_DFLT 0x1f007550 127 128 #define SI_ASI_DFLT 10000 129 #define SI_BSP_DFLT 0x41EB 130 #define SI_BSU_DFLT 0x2 131 #define SI_AH_DFLT 5 132 #define SI_RLP_DFLT 25 133 #define SI_RMP_DFLT 65 134 #define SI_LHP_DFLT 40 135 #define SI_LMP_DFLT 15 136 #define SI_TD_DFLT 0 137 #define SI_UTC_DFLT_00 0x24 138 #define SI_UTC_DFLT_01 0x22 139 #define SI_UTC_DFLT_02 0x22 140 #define SI_UTC_DFLT_03 0x22 141 #define SI_UTC_DFLT_04 0x22 142 #define SI_UTC_DFLT_05 0x22 143 #define SI_UTC_DFLT_06 0x22 144 #define SI_UTC_DFLT_07 0x22 145 #define SI_UTC_DFLT_08 0x22 146 #define SI_UTC_DFLT_09 0x22 147 #define SI_UTC_DFLT_10 0x22 148 #define SI_UTC_DFLT_11 0x22 149 #define SI_UTC_DFLT_12 0x22 150 #define SI_UTC_DFLT_13 0x22 151 #define SI_UTC_DFLT_14 0x22 152 #define SI_DTC_DFLT_00 0x24 153 #define SI_DTC_DFLT_01 0x22 154 #define SI_DTC_DFLT_02 0x22 155 #define SI_DTC_DFLT_03 0x22 156 #define SI_DTC_DFLT_04 0x22 157 #define SI_DTC_DFLT_05 0x22 158 #define SI_DTC_DFLT_06 0x22 159 #define SI_DTC_DFLT_07 0x22 160 #define SI_DTC_DFLT_08 0x22 161 #define SI_DTC_DFLT_09 0x22 162 #define SI_DTC_DFLT_10 0x22 163 #define SI_DTC_DFLT_11 0x22 164 #define SI_DTC_DFLT_12 0x22 165 #define SI_DTC_DFLT_13 0x22 166 #define SI_DTC_DFLT_14 0x22 167 #define SI_VRC_DFLT 0x0000C003 168 #define SI_VOLTAGERESPONSETIME_DFLT 1000 169 #define SI_BACKBIASRESPONSETIME_DFLT 1000 170 #define SI_VRU_DFLT 0x3 171 #define SI_SPLLSTEPTIME_DFLT 0x1000 172 #define SI_SPLLSTEPUNIT_DFLT 0x3 173 #define SI_TPU_DFLT 0 174 #define SI_TPC_DFLT 0x200 175 #define SI_SSTU_DFLT 0 176 #define SI_SST_DFLT 0x00C8 177 #define SI_GICST_DFLT 0x200 178 #define SI_FCT_DFLT 0x0400 179 #define SI_FCTU_DFLT 0 180 #define SI_CTXCGTT3DRPHC_DFLT 0x20 181 #define SI_CTXCGTT3DRSDC_DFLT 0x40 182 #define SI_VDDC3DOORPHC_DFLT 0x100 183 #define SI_VDDC3DOORSDC_DFLT 0x7 184 #define SI_VDDC3DOORSU_DFLT 0 185 #define SI_MPLLLOCKTIME_DFLT 100 186 #define SI_MPLLRESETTIME_DFLT 150 187 #define SI_VCOSTEPPCT_DFLT 20 188 #define SI_ENDINGVCOSTEPPCT_DFLT 5 189 #define SI_REFERENCEDIVIDER_DFLT 4 190 191 #define SI_PM_NUMBER_OF_TC 15 192 #define SI_PM_NUMBER_OF_SCLKS 20 193 #define SI_PM_NUMBER_OF_MCLKS 4 194 #define SI_PM_NUMBER_OF_VOLTAGE_LEVELS 4 195 #define SI_PM_NUMBER_OF_ACTIVITY_LEVELS 3 196 197 /* XXX are these ok? */ 198 #define SI_TEMP_RANGE_MIN (90 * 1000) 199 #define SI_TEMP_RANGE_MAX (120 * 1000) 200 201 #define FDO_PWM_MODE_STATIC 1 202 #define FDO_PWM_MODE_STATIC_RPM 5 203 204 enum ni_dc_cac_level 205 { 206 NISLANDS_DCCAC_LEVEL_0 = 0, 207 NISLANDS_DCCAC_LEVEL_1, 208 NISLANDS_DCCAC_LEVEL_2, 209 NISLANDS_DCCAC_LEVEL_3, 210 NISLANDS_DCCAC_LEVEL_4, 211 NISLANDS_DCCAC_LEVEL_5, 212 NISLANDS_DCCAC_LEVEL_6, 213 NISLANDS_DCCAC_LEVEL_7, 214 NISLANDS_DCCAC_MAX_LEVELS 215 }; 216 217 enum si_cac_config_reg_type 218 { 219 SISLANDS_CACCONFIG_MMR = 0, 220 SISLANDS_CACCONFIG_CGIND, 221 SISLANDS_CACCONFIG_MAX 222 }; 223 224 enum si_power_level { 225 SI_POWER_LEVEL_LOW = 0, 226 SI_POWER_LEVEL_MEDIUM = 1, 227 SI_POWER_LEVEL_HIGH = 2, 228 SI_POWER_LEVEL_CTXSW = 3, 229 }; 230 231 enum si_td { 232 SI_TD_AUTO, 233 SI_TD_UP, 234 SI_TD_DOWN, 235 }; 236 237 enum si_display_watermark { 238 SI_DISPLAY_WATERMARK_LOW = 0, 239 SI_DISPLAY_WATERMARK_HIGH = 1, 240 }; 241 242 enum si_display_gap 243 { 244 SI_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, 245 SI_PM_DISPLAY_GAP_VBLANK = 1, 246 SI_PM_DISPLAY_GAP_WATERMARK = 2, 247 SI_PM_DISPLAY_GAP_IGNORE = 3, 248 }; 249 250 extern const struct amdgpu_ip_block_version si_smu_ip_block; 251 252 struct ni_leakage_coeffients 253 { 254 u32 at; 255 u32 bt; 256 u32 av; 257 u32 bv; 258 s32 t_slope; 259 s32 t_intercept; 260 u32 t_ref; 261 }; 262 263 struct SMC_Evergreen_MCRegisterAddress 264 { 265 uint16_t s0; 266 uint16_t s1; 267 }; 268 269 typedef struct SMC_Evergreen_MCRegisterAddress SMC_Evergreen_MCRegisterAddress; 270 271 struct evergreen_mc_reg_entry { 272 u32 mclk_max; 273 u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 274 }; 275 276 struct evergreen_mc_reg_table { 277 u8 last; 278 u8 num_entries; 279 u16 valid_flag; 280 struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 281 SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 282 }; 283 284 struct SMC_Evergreen_MCRegisterSet 285 { 286 uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 287 }; 288 289 typedef struct SMC_Evergreen_MCRegisterSet SMC_Evergreen_MCRegisterSet; 290 291 struct SMC_Evergreen_MCRegisters 292 { 293 uint8_t last; 294 uint8_t reserved[3]; 295 SMC_Evergreen_MCRegisterAddress address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 296 SMC_Evergreen_MCRegisterSet data[5]; 297 }; 298 299 typedef struct SMC_Evergreen_MCRegisters SMC_Evergreen_MCRegisters; 300 301 struct SMC_NIslands_MCRegisterSet 302 { 303 uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 304 }; 305 306 typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet; 307 308 struct ni_mc_reg_entry { 309 u32 mclk_max; 310 u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 311 }; 312 313 struct SMC_NIslands_MCRegisterAddress 314 { 315 uint16_t s0; 316 uint16_t s1; 317 }; 318 319 typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress; 320 321 struct SMC_NIslands_MCRegisters 322 { 323 uint8_t last; 324 uint8_t reserved[3]; 325 SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 326 SMC_NIslands_MCRegisterSet data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; 327 }; 328 329 typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters; 330 331 struct evergreen_ulv_param { 332 bool supported; 333 struct rv7xx_pl *pl; 334 }; 335 336 struct evergreen_arb_registers { 337 u32 mc_arb_dram_timing; 338 u32 mc_arb_dram_timing2; 339 u32 mc_arb_rfsh_rate; 340 u32 mc_arb_burst_time; 341 }; 342 343 struct at { 344 u32 rlp; 345 u32 rmp; 346 u32 lhp; 347 u32 lmp; 348 }; 349 350 struct ni_clock_registers { 351 u32 cg_spll_func_cntl; 352 u32 cg_spll_func_cntl_2; 353 u32 cg_spll_func_cntl_3; 354 u32 cg_spll_func_cntl_4; 355 u32 cg_spll_spread_spectrum; 356 u32 cg_spll_spread_spectrum_2; 357 u32 mclk_pwrmgt_cntl; 358 u32 dll_cntl; 359 u32 mpll_ad_func_cntl; 360 u32 mpll_ad_func_cntl_2; 361 u32 mpll_dq_func_cntl; 362 u32 mpll_dq_func_cntl_2; 363 u32 mpll_ss1; 364 u32 mpll_ss2; 365 }; 366 367 struct RV770_SMC_SCLK_VALUE 368 { 369 uint32_t vCG_SPLL_FUNC_CNTL; 370 uint32_t vCG_SPLL_FUNC_CNTL_2; 371 uint32_t vCG_SPLL_FUNC_CNTL_3; 372 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 373 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 374 uint32_t sclk_value; 375 }; 376 377 typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE; 378 379 struct RV770_SMC_MCLK_VALUE 380 { 381 uint32_t vMPLL_AD_FUNC_CNTL; 382 uint32_t vMPLL_AD_FUNC_CNTL_2; 383 uint32_t vMPLL_DQ_FUNC_CNTL; 384 uint32_t vMPLL_DQ_FUNC_CNTL_2; 385 uint32_t vMCLK_PWRMGT_CNTL; 386 uint32_t vDLL_CNTL; 387 uint32_t vMPLL_SS; 388 uint32_t vMPLL_SS2; 389 uint32_t mclk_value; 390 }; 391 392 typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE; 393 394 395 struct RV730_SMC_MCLK_VALUE 396 { 397 uint32_t vMCLK_PWRMGT_CNTL; 398 uint32_t vDLL_CNTL; 399 uint32_t vMPLL_FUNC_CNTL; 400 uint32_t vMPLL_FUNC_CNTL2; 401 uint32_t vMPLL_FUNC_CNTL3; 402 uint32_t vMPLL_SS; 403 uint32_t vMPLL_SS2; 404 uint32_t mclk_value; 405 }; 406 407 typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE; 408 409 struct RV770_SMC_VOLTAGE_VALUE 410 { 411 uint16_t value; 412 uint8_t index; 413 uint8_t padding; 414 }; 415 416 typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE; 417 418 union RV7XX_SMC_MCLK_VALUE 419 { 420 RV770_SMC_MCLK_VALUE mclk770; 421 RV730_SMC_MCLK_VALUE mclk730; 422 }; 423 424 typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE; 425 426 struct RV770_SMC_HW_PERFORMANCE_LEVEL 427 { 428 uint8_t arbValue; 429 union{ 430 uint8_t seqValue; 431 uint8_t ACIndex; 432 }; 433 uint8_t displayWatermark; 434 uint8_t gen2PCIE; 435 uint8_t gen2XSP; 436 uint8_t backbias; 437 uint8_t strobeMode; 438 uint8_t mcFlags; 439 uint32_t aT; 440 uint32_t bSP; 441 RV770_SMC_SCLK_VALUE sclk; 442 RV7XX_SMC_MCLK_VALUE mclk; 443 RV770_SMC_VOLTAGE_VALUE vddc; 444 RV770_SMC_VOLTAGE_VALUE mvdd; 445 RV770_SMC_VOLTAGE_VALUE vddci; 446 uint8_t reserved1; 447 uint8_t reserved2; 448 uint8_t stateFlags; 449 uint8_t padding; 450 }; 451 452 typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL; 453 454 struct RV770_SMC_SWSTATE 455 { 456 uint8_t flags; 457 uint8_t padding1; 458 uint8_t padding2; 459 uint8_t padding3; 460 RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 461 }; 462 463 typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE; 464 465 struct RV770_SMC_VOLTAGEMASKTABLE 466 { 467 uint8_t highMask[RV770_SMC_VOLTAGEMASK_MAX]; 468 uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX]; 469 }; 470 471 typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE; 472 473 struct RV770_SMC_STATETABLE 474 { 475 uint8_t thermalProtectType; 476 uint8_t systemFlags; 477 uint8_t maxVDDCIndexInPPTable; 478 uint8_t extraFlags; 479 uint8_t highSMIO[MAX_NO_VREG_STEPS]; 480 uint32_t lowSMIO[MAX_NO_VREG_STEPS]; 481 RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable; 482 RV770_SMC_SWSTATE initialState; 483 RV770_SMC_SWSTATE ACPIState; 484 RV770_SMC_SWSTATE driverState; 485 RV770_SMC_SWSTATE ULVState; 486 }; 487 488 typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE; 489 490 struct vddc_table_entry { 491 u16 vddc; 492 u8 vddc_index; 493 u8 high_smio; 494 u32 low_smio; 495 }; 496 497 struct rv770_clock_registers { 498 u32 cg_spll_func_cntl; 499 u32 cg_spll_func_cntl_2; 500 u32 cg_spll_func_cntl_3; 501 u32 cg_spll_spread_spectrum; 502 u32 cg_spll_spread_spectrum_2; 503 u32 mpll_ad_func_cntl; 504 u32 mpll_ad_func_cntl_2; 505 u32 mpll_dq_func_cntl; 506 u32 mpll_dq_func_cntl_2; 507 u32 mclk_pwrmgt_cntl; 508 u32 dll_cntl; 509 u32 mpll_ss1; 510 u32 mpll_ss2; 511 }; 512 513 struct rv730_clock_registers { 514 u32 cg_spll_func_cntl; 515 u32 cg_spll_func_cntl_2; 516 u32 cg_spll_func_cntl_3; 517 u32 cg_spll_spread_spectrum; 518 u32 cg_spll_spread_spectrum_2; 519 u32 mclk_pwrmgt_cntl; 520 u32 dll_cntl; 521 u32 mpll_func_cntl; 522 u32 mpll_func_cntl2; 523 u32 mpll_func_cntl3; 524 u32 mpll_ss; 525 u32 mpll_ss2; 526 }; 527 528 union r7xx_clock_registers { 529 struct rv770_clock_registers rv770; 530 struct rv730_clock_registers rv730; 531 }; 532 533 struct rv7xx_power_info { 534 /* flags */ 535 bool mem_gddr5; 536 bool pcie_gen2; 537 bool dynamic_pcie_gen2; 538 bool acpi_pcie_gen2; 539 bool boot_in_gen2; 540 bool voltage_control; /* vddc */ 541 bool mvdd_control; 542 bool sclk_ss; 543 bool mclk_ss; 544 bool dynamic_ss; 545 bool gfx_clock_gating; 546 bool mg_clock_gating; 547 bool mgcgtssm; 548 bool power_gating; 549 bool thermal_protection; 550 bool display_gap; 551 bool dcodt; 552 bool ulps; 553 /* registers */ 554 union r7xx_clock_registers clk_regs; 555 u32 s0_vid_lower_smio_cntl; 556 /* voltage */ 557 u32 vddc_mask_low; 558 u32 mvdd_mask_low; 559 u32 mvdd_split_frequency; 560 u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES]; 561 u16 max_vddc; 562 u16 max_vddc_in_table; 563 u16 min_vddc_in_table; 564 struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS]; 565 u8 valid_vddc_entries; 566 /* dc odt */ 567 u32 mclk_odt_threshold; 568 u8 odt_value_0[2]; 569 u8 odt_value_1[2]; 570 /* stored values */ 571 u32 boot_sclk; 572 u16 acpi_vddc; 573 u32 ref_div; 574 u32 active_auto_throttle_sources; 575 u32 mclk_stutter_mode_threshold; 576 u32 mclk_strobe_mode_threshold; 577 u32 mclk_edc_enable_threshold; 578 u32 bsp; 579 u32 bsu; 580 u32 pbsp; 581 u32 pbsu; 582 u32 dsp; 583 u32 psp; 584 u32 asi; 585 u32 pasi; 586 u32 vrc; 587 u32 restricted_levels; 588 u32 rlp; 589 u32 rmp; 590 u32 lhp; 591 u32 lmp; 592 /* smc offsets */ 593 u16 state_table_start; 594 u16 soft_regs_start; 595 u16 sram_end; 596 /* scratch structs */ 597 RV770_SMC_STATETABLE smc_statetable; 598 }; 599 600 struct rv7xx_pl { 601 u32 sclk; 602 u32 mclk; 603 u16 vddc; 604 u16 vddci; /* eg+ only */ 605 u32 flags; 606 enum amdgpu_pcie_gen pcie_gen; /* si+ only */ 607 }; 608 609 struct rv7xx_ps { 610 struct rv7xx_pl high; 611 struct rv7xx_pl medium; 612 struct rv7xx_pl low; 613 bool dc_compatible; 614 }; 615 616 struct si_ps { 617 u16 performance_level_count; 618 bool dc_compatible; 619 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 620 }; 621 622 struct ni_mc_reg_table { 623 u8 last; 624 u8 num_entries; 625 u16 valid_flag; 626 struct ni_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 627 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 628 }; 629 630 struct ni_cac_data 631 { 632 struct ni_leakage_coeffients leakage_coefficients; 633 u32 i_leakage; 634 s32 leakage_minimum_temperature; 635 u32 pwr_const; 636 u32 dc_cac_value; 637 u32 bif_cac_value; 638 u32 lkge_pwr; 639 u8 mc_wr_weight; 640 u8 mc_rd_weight; 641 u8 allow_ovrflw; 642 u8 num_win_tdp; 643 u8 l2num_win_tdp; 644 u8 lts_truncate_n; 645 }; 646 647 struct evergreen_power_info { 648 /* must be first! */ 649 struct rv7xx_power_info rv7xx; 650 /* flags */ 651 bool vddci_control; 652 bool dynamic_ac_timing; 653 bool abm; 654 bool mcls; 655 bool light_sleep; 656 bool memory_transition; 657 bool pcie_performance_request; 658 bool pcie_performance_request_registered; 659 bool sclk_deep_sleep; 660 bool dll_default_on; 661 bool ls_clock_gating; 662 bool smu_uvd_hs; 663 bool uvd_enabled; 664 /* stored values */ 665 u16 acpi_vddci; 666 u8 mvdd_high_index; 667 u8 mvdd_low_index; 668 u32 mclk_edc_wr_enable_threshold; 669 struct evergreen_mc_reg_table mc_reg_table; 670 struct atom_voltage_table vddc_voltage_table; 671 struct atom_voltage_table vddci_voltage_table; 672 struct evergreen_arb_registers bootup_arb_registers; 673 struct evergreen_ulv_param ulv; 674 struct at ats[2]; 675 /* smc offsets */ 676 u16 mc_reg_table_start; 677 struct amdgpu_ps current_rps; 678 struct rv7xx_ps current_ps; 679 struct amdgpu_ps requested_rps; 680 struct rv7xx_ps requested_ps; 681 }; 682 683 struct PP_NIslands_Dpm2PerfLevel 684 { 685 uint8_t MaxPS; 686 uint8_t TgtAct; 687 uint8_t MaxPS_StepInc; 688 uint8_t MaxPS_StepDec; 689 uint8_t PSST; 690 uint8_t NearTDPDec; 691 uint8_t AboveSafeInc; 692 uint8_t BelowSafeInc; 693 uint8_t PSDeltaLimit; 694 uint8_t PSDeltaWin; 695 uint8_t Reserved[6]; 696 }; 697 698 typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel; 699 700 struct PP_NIslands_DPM2Parameters 701 { 702 uint32_t TDPLimit; 703 uint32_t NearTDPLimit; 704 uint32_t SafePowerLimit; 705 uint32_t PowerBoostLimit; 706 }; 707 typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters; 708 709 struct NISLANDS_SMC_SCLK_VALUE 710 { 711 uint32_t vCG_SPLL_FUNC_CNTL; 712 uint32_t vCG_SPLL_FUNC_CNTL_2; 713 uint32_t vCG_SPLL_FUNC_CNTL_3; 714 uint32_t vCG_SPLL_FUNC_CNTL_4; 715 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 716 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 717 uint32_t sclk_value; 718 }; 719 720 typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE; 721 722 struct NISLANDS_SMC_MCLK_VALUE 723 { 724 uint32_t vMPLL_FUNC_CNTL; 725 uint32_t vMPLL_FUNC_CNTL_1; 726 uint32_t vMPLL_FUNC_CNTL_2; 727 uint32_t vMPLL_AD_FUNC_CNTL; 728 uint32_t vMPLL_AD_FUNC_CNTL_2; 729 uint32_t vMPLL_DQ_FUNC_CNTL; 730 uint32_t vMPLL_DQ_FUNC_CNTL_2; 731 uint32_t vMCLK_PWRMGT_CNTL; 732 uint32_t vDLL_CNTL; 733 uint32_t vMPLL_SS; 734 uint32_t vMPLL_SS2; 735 uint32_t mclk_value; 736 }; 737 738 typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE; 739 740 struct NISLANDS_SMC_VOLTAGE_VALUE 741 { 742 uint16_t value; 743 uint8_t index; 744 uint8_t padding; 745 }; 746 747 typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE; 748 749 struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL 750 { 751 uint8_t arbValue; 752 uint8_t ACIndex; 753 uint8_t displayWatermark; 754 uint8_t gen2PCIE; 755 uint8_t reserved1; 756 uint8_t reserved2; 757 uint8_t strobeMode; 758 uint8_t mcFlags; 759 uint32_t aT; 760 uint32_t bSP; 761 NISLANDS_SMC_SCLK_VALUE sclk; 762 NISLANDS_SMC_MCLK_VALUE mclk; 763 NISLANDS_SMC_VOLTAGE_VALUE vddc; 764 NISLANDS_SMC_VOLTAGE_VALUE mvdd; 765 NISLANDS_SMC_VOLTAGE_VALUE vddci; 766 NISLANDS_SMC_VOLTAGE_VALUE std_vddc; 767 uint32_t powergate_en; 768 uint8_t hUp; 769 uint8_t hDown; 770 uint8_t stateFlags; 771 uint8_t arbRefreshState; 772 uint32_t SQPowerThrottle; 773 uint32_t SQPowerThrottle_2; 774 uint32_t reserved[2]; 775 PP_NIslands_Dpm2PerfLevel dpm2; 776 }; 777 778 typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL; 779 780 struct NISLANDS_SMC_SWSTATE 781 { 782 uint8_t flags; 783 uint8_t levelCount; 784 uint8_t padding2; 785 uint8_t padding3; 786 NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1]; 787 }; 788 789 typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE; 790 791 struct NISLANDS_SMC_VOLTAGEMASKTABLE 792 { 793 uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 794 uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 795 }; 796 797 typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE; 798 799 #define NISLANDS_MAX_NO_VREG_STEPS 32 800 801 struct NISLANDS_SMC_STATETABLE 802 { 803 uint8_t thermalProtectType; 804 uint8_t systemFlags; 805 uint8_t maxVDDCIndexInPPTable; 806 uint8_t extraFlags; 807 uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 808 uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 809 NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; 810 PP_NIslands_DPM2Parameters dpm2Params; 811 NISLANDS_SMC_SWSTATE initialState; 812 NISLANDS_SMC_SWSTATE ACPIState; 813 NISLANDS_SMC_SWSTATE ULVState; 814 NISLANDS_SMC_SWSTATE driverState; 815 NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1]; 816 }; 817 818 typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE; 819 820 struct ni_power_info { 821 /* must be first! */ 822 struct evergreen_power_info eg; 823 struct ni_clock_registers clock_registers; 824 struct ni_mc_reg_table mc_reg_table; 825 u32 mclk_rtt_mode_threshold; 826 /* flags */ 827 bool use_power_boost_limit; 828 bool support_cac_long_term_average; 829 bool cac_enabled; 830 bool cac_configuration_required; 831 bool driver_calculate_cac_leakage; 832 bool pc_enabled; 833 bool enable_power_containment; 834 bool enable_cac; 835 bool enable_sq_ramping; 836 /* smc offsets */ 837 u16 arb_table_start; 838 u16 fan_table_start; 839 u16 cac_table_start; 840 u16 spll_table_start; 841 /* CAC stuff */ 842 struct ni_cac_data cac_data; 843 u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS]; 844 const struct ni_cac_weights *cac_weights; 845 u8 lta_window_size; 846 u8 lts_truncate; 847 struct si_ps current_ps; 848 struct si_ps requested_ps; 849 /* scratch structs */ 850 SMC_NIslands_MCRegisters smc_mc_reg_table; 851 NISLANDS_SMC_STATETABLE smc_statetable; 852 }; 853 854 struct si_cac_config_reg 855 { 856 u32 offset; 857 u32 mask; 858 u32 shift; 859 u32 value; 860 enum si_cac_config_reg_type type; 861 }; 862 863 struct si_powertune_data 864 { 865 u32 cac_window; 866 u32 l2_lta_window_size_default; 867 u8 lts_truncate_default; 868 u8 shift_n_default; 869 u8 operating_temp; 870 struct ni_leakage_coeffients leakage_coefficients; 871 u32 fixed_kt; 872 u32 lkge_lut_v0_percent; 873 u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS]; 874 bool enable_powertune_by_default; 875 }; 876 877 struct si_dyn_powertune_data 878 { 879 u32 cac_leakage; 880 s32 leakage_minimum_temperature; 881 u32 wintime; 882 u32 l2_lta_window_size; 883 u8 lts_truncate; 884 u8 shift_n; 885 u8 dc_pwr_value; 886 bool disable_uvd_powertune; 887 }; 888 889 struct si_dte_data 890 { 891 u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 892 u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 893 u32 k; 894 u32 t0; 895 u32 max_t; 896 u8 window_size; 897 u8 temp_select; 898 u8 dte_mode; 899 u8 tdep_count; 900 u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 901 u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 902 u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 903 u32 t_threshold; 904 bool enable_dte_by_default; 905 }; 906 907 struct si_clock_registers { 908 u32 cg_spll_func_cntl; 909 u32 cg_spll_func_cntl_2; 910 u32 cg_spll_func_cntl_3; 911 u32 cg_spll_func_cntl_4; 912 u32 cg_spll_spread_spectrum; 913 u32 cg_spll_spread_spectrum_2; 914 u32 dll_cntl; 915 u32 mclk_pwrmgt_cntl; 916 u32 mpll_ad_func_cntl; 917 u32 mpll_dq_func_cntl; 918 u32 mpll_func_cntl; 919 u32 mpll_func_cntl_1; 920 u32 mpll_func_cntl_2; 921 u32 mpll_ss1; 922 u32 mpll_ss2; 923 }; 924 925 struct si_mc_reg_entry { 926 u32 mclk_max; 927 u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 928 }; 929 930 struct si_mc_reg_table { 931 u8 last; 932 u8 num_entries; 933 u16 valid_flag; 934 struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 935 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 936 }; 937 938 struct si_leakage_voltage_entry 939 { 940 u16 voltage; 941 u16 leakage_index; 942 }; 943 944 struct si_leakage_voltage 945 { 946 u16 count; 947 struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT]; 948 }; 949 950 951 struct si_ulv_param { 952 bool supported; 953 u32 cg_ulv_control; 954 u32 cg_ulv_parameter; 955 u32 volt_change_delay; 956 struct rv7xx_pl pl; 957 bool one_pcie_lane_in_ulv; 958 }; 959 960 struct si_power_info { 961 /* must be first! */ 962 struct ni_power_info ni; 963 struct si_clock_registers clock_registers; 964 struct si_mc_reg_table mc_reg_table; 965 struct atom_voltage_table mvdd_voltage_table; 966 struct atom_voltage_table vddc_phase_shed_table; 967 struct si_leakage_voltage leakage_voltage; 968 u16 mvdd_bootup_value; 969 struct si_ulv_param ulv; 970 u32 max_cu; 971 /* pcie gen */ 972 enum amdgpu_pcie_gen force_pcie_gen; 973 enum amdgpu_pcie_gen boot_pcie_gen; 974 enum amdgpu_pcie_gen acpi_pcie_gen; 975 u32 sys_pcie_mask; 976 /* flags */ 977 bool enable_dte; 978 bool enable_ppm; 979 bool vddc_phase_shed_control; 980 bool pspp_notify_required; 981 bool sclk_deep_sleep_above_low; 982 bool voltage_control_svi2; 983 bool vddci_control_svi2; 984 /* smc offsets */ 985 u32 sram_end; 986 u32 state_table_start; 987 u32 soft_regs_start; 988 u32 mc_reg_table_start; 989 u32 arb_table_start; 990 u32 cac_table_start; 991 u32 dte_table_start; 992 u32 spll_table_start; 993 u32 papm_cfg_table_start; 994 u32 fan_table_start; 995 /* CAC stuff */ 996 const struct si_cac_config_reg *cac_weights; 997 const struct si_cac_config_reg *lcac_config; 998 const struct si_cac_config_reg *cac_override; 999 const struct si_powertune_data *powertune_data; 1000 struct si_dyn_powertune_data dyn_powertune_data; 1001 /* DTE stuff */ 1002 struct si_dte_data dte_data; 1003 /* scratch structs */ 1004 SMC_SIslands_MCRegisters smc_mc_reg_table; 1005 SISLANDS_SMC_STATETABLE smc_statetable; 1006 PP_SIslands_PAPMParameters papm_parm; 1007 /* SVI2 */ 1008 u8 svd_gpio_id; 1009 u8 svc_gpio_id; 1010 /* fan control */ 1011 bool fan_ctrl_is_in_default_mode; 1012 u32 t_min; 1013 u32 fan_ctrl_default_mode; 1014 bool fan_is_controlled_by_smc; 1015 }; 1016 1017 #endif 1018
Indexes created Sat Sep 20 22:09:52 GMT 2025