1 /* $NetBSD: mesongxl_pinctrl.c,v 1.1 2019/04/19 19:07:56 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: mesongxl_pinctrl.c,v 1.1 2019/04/19 19:07:56 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 34 #include <arm/amlogic/meson_pinctrl.h> 35 36 /* CBUS pinmux registers */ 37 #define CBUS_REG(n) ((n) << 2) 38 #define REG0 CBUS_REG(0) 39 #define REG1 CBUS_REG(1) 40 #define REG2 CBUS_REG(2) 41 #define REG3 CBUS_REG(3) 42 #define REG4 CBUS_REG(4) 43 #define REG5 CBUS_REG(5) 44 #define REG6 CBUS_REG(6) 45 #define REG7 CBUS_REG(7) 46 #define REG8 CBUS_REG(8) 47 #define REG9 CBUS_REG(9) 48 49 /* AO pinmux registers */ 50 #define AOREG0 0x00 51 #define AOREG1 0x04 52 53 /* 54 * GPIO banks. The values must match those in dt-bindings/gpio/meson-gxl-gpio.h 55 */ 56 enum { 57 GPIOZ_0 = 0, 58 GPIOZ_1, 59 GPIOZ_2, 60 GPIOZ_3, 61 GPIOZ_4, 62 GPIOZ_5, 63 GPIOZ_6, 64 GPIOZ_7, 65 GPIOZ_8, 66 GPIOZ_9, 67 GPIOZ_10, 68 GPIOZ_11, 69 GPIOZ_12, 70 GPIOZ_13, 71 GPIOZ_14, 72 GPIOZ_15, 73 74 GPIOH_0 = 16, 75 GPIOH_1, 76 GPIOH_2, 77 GPIOH_3, 78 GPIOH_4, 79 GPIOH_5, 80 GPIOH_6, 81 GPIOH_7, 82 GPIOH_8, 83 GPIOH_9, 84 85 BOOT_0 = 26, 86 BOOT_1, 87 BOOT_2, 88 BOOT_3, 89 BOOT_4, 90 BOOT_5, 91 BOOT_6, 92 BOOT_7, 93 BOOT_8, 94 BOOT_9, 95 BOOT_10, 96 BOOT_11, 97 BOOT_12, 98 BOOT_13, 99 BOOT_14, 100 BOOT_15, 101 102 CARD_0 = 42, 103 CARD_1, 104 CARD_2, 105 CARD_3, 106 CARD_4, 107 CARD_5, 108 CARD_6, 109 110 GPIODV_0 = 49, 111 GPIODV_1, 112 GPIODV_2, 113 GPIODV_3, 114 GPIODV_4, 115 GPIODV_5, 116 GPIODV_6, 117 GPIODV_7, 118 GPIODV_8, 119 GPIODV_9, 120 GPIODV_10, 121 GPIODV_11, 122 GPIODV_12, 123 GPIODV_13, 124 GPIODV_14, 125 GPIODV_15, 126 GPIODV_16, 127 GPIODV_17, 128 GPIODV_18, 129 GPIODV_19, 130 GPIODV_20, 131 GPIODV_21, 132 GPIODV_22, 133 GPIODV_23, 134 GPIODV_24, 135 GPIODV_25, 136 GPIODV_26, 137 GPIODV_27, 138 GPIODV_28, 139 GPIODV_29, 140 141 GPIOX_0 = 79, 142 GPIOX_1, 143 GPIOX_2, 144 GPIOX_3, 145 GPIOX_4, 146 GPIOX_5, 147 GPIOX_6, 148 GPIOX_7, 149 GPIOX_8, 150 GPIOX_9, 151 GPIOX_10, 152 GPIOX_11, 153 GPIOX_12, 154 GPIOX_13, 155 GPIOX_14, 156 GPIOX_15, 157 GPIOX_16, 158 GPIOX_17, 159 GPIOX_18, 160 161 GPIOCLK_0 = 98, 162 GPIOCLK_1, 163 164 GPIOAO_0 = 0, 165 GPIOAO_1, 166 GPIOAO_2, 167 GPIOAO_3, 168 GPIOAO_4, 169 GPIOAO_5, 170 GPIOAO_6, 171 GPIOAO_7, 172 GPIOAO_8, 173 GPIOAO_9, 174 GPIO_TEST_N, 175 }; 176 177 #define CBUS_GPIO(_id, _off, _bit) \ 178 [_id] = { \ 179 .id = (_id), \ 180 .name = __STRING(_id), \ 181 .oen = { \ 182 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 183 .reg = CBUS_REG((_off) * 3 + 0), \ 184 .mask = __BIT(_bit) \ 185 }, \ 186 .out = { \ 187 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 188 .reg = CBUS_REG((_off) * 3 + 1), \ 189 .mask = __BIT(_bit) \ 190 }, \ 191 .in = { \ 192 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 193 .reg = CBUS_REG((_off) * 3 + 2), \ 194 .mask = __BIT(_bit) \ 195 }, \ 196 .pupden = { \ 197 .type = MESON_PINCTRL_REGTYPE_PULL_ENABLE, \ 198 .reg = CBUS_REG(_off), \ 199 .mask = __BIT(_bit) \ 200 }, \ 201 .pupd = { \ 202 .type = MESON_PINCTRL_REGTYPE_PULL, \ 203 .reg = CBUS_REG(_off), \ 204 .mask = __BIT(_bit) \ 205 }, \ 206 } 207 208 static const struct meson_pinctrl_gpio mesongxl_periphs_gpios[] = { 209 /* GPIODV */ 210 CBUS_GPIO(GPIODV_24, 0, 24), 211 CBUS_GPIO(GPIODV_25, 0, 25), 212 CBUS_GPIO(GPIODV_26, 0, 26), 213 CBUS_GPIO(GPIODV_27, 0, 27), 214 CBUS_GPIO(GPIODV_28, 0, 28), 215 CBUS_GPIO(GPIODV_29, 0, 29), 216 217 /* GPIOH */ 218 CBUS_GPIO(GPIOH_0, 1, 20), 219 CBUS_GPIO(GPIOH_1, 1, 21), 220 CBUS_GPIO(GPIOH_2, 1, 22), 221 CBUS_GPIO(GPIOH_3, 1, 23), 222 CBUS_GPIO(GPIOH_4, 1, 24), 223 CBUS_GPIO(GPIOH_5, 1, 25), 224 CBUS_GPIO(GPIOH_6, 1, 26), 225 CBUS_GPIO(GPIOH_7, 1, 27), 226 CBUS_GPIO(GPIOH_8, 1, 28), 227 CBUS_GPIO(GPIOH_9, 1, 29), 228 229 /* BOOT */ 230 CBUS_GPIO(BOOT_0, 2, 0), 231 CBUS_GPIO(BOOT_1, 2, 1), 232 CBUS_GPIO(BOOT_2, 2, 2), 233 CBUS_GPIO(BOOT_3, 2, 3), 234 CBUS_GPIO(BOOT_4, 2, 4), 235 CBUS_GPIO(BOOT_5, 2, 5), 236 CBUS_GPIO(BOOT_6, 2, 6), 237 CBUS_GPIO(BOOT_7, 2, 7), 238 CBUS_GPIO(BOOT_8, 2, 8), 239 CBUS_GPIO(BOOT_9, 2, 9), 240 CBUS_GPIO(BOOT_10, 2, 10), 241 CBUS_GPIO(BOOT_11, 2, 11), 242 CBUS_GPIO(BOOT_12, 2, 12), 243 CBUS_GPIO(BOOT_13, 2, 13), 244 CBUS_GPIO(BOOT_14, 2, 14), 245 CBUS_GPIO(BOOT_15, 2, 15), 246 247 /* CARD */ 248 CBUS_GPIO(CARD_0, 2, 20), 249 CBUS_GPIO(CARD_1, 2, 21), 250 CBUS_GPIO(CARD_2, 2, 22), 251 CBUS_GPIO(CARD_3, 2, 23), 252 CBUS_GPIO(CARD_4, 2, 24), 253 CBUS_GPIO(CARD_5, 2, 25), 254 CBUS_GPIO(CARD_6, 2, 26), 255 256 /* GPIOCLK */ 257 CBUS_GPIO(GPIOCLK_0, 3, 28), 258 CBUS_GPIO(GPIOCLK_1, 3, 29), 259 260 /* GPIOX */ 261 CBUS_GPIO(GPIOX_0, 4, 0), 262 CBUS_GPIO(GPIOX_1, 4, 1), 263 CBUS_GPIO(GPIOX_2, 4, 2), 264 CBUS_GPIO(GPIOX_3, 4, 3), 265 CBUS_GPIO(GPIOX_4, 4, 4), 266 CBUS_GPIO(GPIOX_5, 4, 5), 267 CBUS_GPIO(GPIOX_6, 4, 6), 268 CBUS_GPIO(GPIOX_7, 4, 7), 269 CBUS_GPIO(GPIOX_8, 4, 8), 270 CBUS_GPIO(GPIOX_9, 4, 9), 271 CBUS_GPIO(GPIOX_10, 4, 10), 272 CBUS_GPIO(GPIOX_11, 4, 11), 273 CBUS_GPIO(GPIOX_12, 4, 12), 274 CBUS_GPIO(GPIOX_13, 4, 13), 275 CBUS_GPIO(GPIOX_14, 4, 14), 276 CBUS_GPIO(GPIOX_15, 4, 15), 277 CBUS_GPIO(GPIOX_16, 4, 16), 278 CBUS_GPIO(GPIOX_17, 4, 17), 279 CBUS_GPIO(GPIOX_18, 4, 18), 280 }; 281 282 #define AO_GPIO(_id, _bit) \ 283 [_id] = { \ 284 .id = (_id), \ 285 .name = __STRING(_id), \ 286 .oen = { \ 287 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 288 .reg = 0, \ 289 .mask = __BIT(_bit) \ 290 }, \ 291 .out = { \ 292 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 293 .reg = 0, \ 294 .mask = __BIT(_bit + 16) \ 295 }, \ 296 .in = { \ 297 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 298 .reg = 4, \ 299 .mask = __BIT(_bit) \ 300 }, \ 301 .pupden = { \ 302 .type = MESON_PINCTRL_REGTYPE_PULL, \ 303 .reg = 0, \ 304 .mask = __BIT(_bit) \ 305 }, \ 306 .pupd = { \ 307 .type = MESON_PINCTRL_REGTYPE_PULL, \ 308 .reg = 0, \ 309 .mask = __BIT(_bit + 16) \ 310 }, \ 311 } 312 313 static const struct meson_pinctrl_gpio mesongxl_aobus_gpios[] = { 314 /* GPIOAO */ 315 AO_GPIO(GPIOAO_0, 0), 316 AO_GPIO(GPIOAO_1, 1), 317 AO_GPIO(GPIOAO_2, 2), 318 AO_GPIO(GPIOAO_3, 3), 319 AO_GPIO(GPIOAO_4, 4), 320 AO_GPIO(GPIOAO_5, 5), 321 AO_GPIO(GPIOAO_6, 6), 322 AO_GPIO(GPIOAO_7, 7), 323 AO_GPIO(GPIOAO_8, 8), 324 AO_GPIO(GPIOAO_9, 9), 325 }; 326 327 static const struct meson_pinctrl_group mesongxl_periphs_groups[] = { 328 /* GPIOX */ 329 { "sdio_d0", REG5, 31, { GPIOX_0 }, 1 }, 330 { "sdio_d1", REG5, 30, { GPIOX_1 }, 1 }, 331 { "sdio_d2", REG5, 29, { GPIOX_2 }, 1 }, 332 { "sdio_d3", REG5, 28, { GPIOX_3 }, 1 }, 333 { "sdio_clk", REG5, 27, { GPIOX_4 }, 1 }, 334 { "sdio_cmd", REG5, 26, { GPIOX_5 }, 1 }, 335 { "sdio_irq", REG5, 24, { GPIOX_7 }, 1 }, 336 { "uart_tx_a", REG5, 19, { GPIOX_12 }, 1 }, 337 { "uart_rx_a", REG5, 18, { GPIOX_13 }, 1 }, 338 { "uart_cts_a", REG5, 17, { GPIOX_14 }, 1 }, 339 { "uart_dts_a", REG5, 16, { GPIOX_15 }, 1 }, 340 { "uart_tx_c", REG5, 13, { GPIOX_8 }, 1 }, 341 { "uart_rx_c", REG5, 12, { GPIOX_9 }, 1 }, 342 { "uart_cts_c", REG5, 11, { GPIOX_10 }, 1 }, 343 { "uart_dts_c", REG5, 10, { GPIOX_11 }, 1 }, 344 { "pwm_a", REG5, 25, { GPIOX_6 }, 1 }, 345 { "pwm_e", REG5, 15, { GPIOX_16 }, 1 }, 346 { "pwm_f_x", REG5, 14, { GPIOX_7 }, 1 }, 347 { "spi_mosi", REG5, 3, { GPIOX_8 }, 1 }, 348 { "spi_miso", REG5, 2, { GPIOX_9 }, 1 }, 349 { "spi_ss0", REG5, 1, { GPIOX_10 }, 1 }, 350 { "spi_sclk", REG5, 0, { GPIOX_11 }, 1 }, 351 352 /* GPIOZ */ 353 { "eth_mdio", REG4, 23, { GPIOZ_0 }, 1 }, 354 { "eth_mdc", REG4, 22, { GPIOZ_1 }, 1 }, 355 { "eth_clk_rx_clk", REG4, 21, { GPIOZ_2 }, 1 }, 356 { "eth_rx_dv", REG4, 20, { GPIOZ_3 }, 1 }, 357 { "eth_rxd0", REG4, 19, { GPIOZ_4 }, 1 }, 358 { "eth_rxd1", REG4, 18, { GPIOZ_5 }, 1 }, 359 { "eth_rxd2", REG4, 17, { GPIOZ_6 }, 1 }, 360 { "eth_rxd3", REG4, 16, { GPIOZ_7 }, 1 }, 361 { "eth_rgmii_tx_clk", REG4, 15, { GPIOZ_8 }, 1 }, 362 { "eth_tx_en", REG4, 14, { GPIOZ_9 }, 1 }, 363 { "eth_txd0", REG4, 13, { GPIOZ_10 }, 1 }, 364 { "eth_txd1", REG4, 12, { GPIOZ_11 }, 1 }, 365 { "eth_txd2", REG4, 11, { GPIOZ_12 }, 1 }, 366 { "eth_txd3", REG4, 10, { GPIOZ_13 }, 1 }, 367 { "pwm_c", REG3, 20, { GPIOZ_15 }, 1 }, 368 { "i2s_out_ch23_z", REG3, 26, { GPIOZ_5 }, 1 }, 369 { "i2s_out_ch45_z", REG3, 25, { GPIOZ_6 }, 1 }, 370 { "i2s_out_ch67_z", REG3, 24, { GPIOZ_7 }, 1 }, 371 { "eth_link_led", REG4, 25, { GPIOZ_14 }, 1 }, 372 { "eth_act_led", REG4, 24, { GPIOZ_15 }, 1 }, 373 374 /* GPIOH */ 375 { "hdmi_hpd", REG6, 31, { GPIOH_0 }, 1 }, 376 { "hdmi_sda", REG6, 30, { GPIOH_1 }, 1 }, 377 { "hdmi_scl", REG6, 29, { GPIOH_2 }, 1 }, 378 { "i2s_am_clk", REG6, 26, { GPIOH_6 }, 1 }, 379 { "i2s_out_ao_clk", REG6, 25, { GPIOH_7 }, 1 }, 380 { "i2s_out_lr_clk", REG6, 24, { GPIOH_8 }, 1 }, 381 { "i2s_out_ch01", REG6, 23, { GPIOH_9 }, 1 }, 382 { "spdif_out_h", REG6, 28, { GPIOH_4 }, 1 }, 383 384 /* GPIODV */ 385 { "uart_tx_b", REG2, 16, { GPIODV_24 }, 1 }, 386 { "uart_rx_b", REG2, 15, { GPIODV_25 }, 1 }, 387 { "uart_cts_b", REG2, 14, { GPIODV_26 }, 1 }, 388 { "uart_rts_b", REG2, 13, { GPIODV_27 }, 1 }, 389 { "i2c_sda_c_dv18", REG1, 17, { GPIODV_18 }, 1 }, 390 { "i2c_sck_c_dv19", REG1, 16, { GPIODV_19 }, 1 }, 391 { "i2c_sda_a", REG1, 15, { GPIODV_24 }, 1 }, 392 { "i2c_sck_a", REG1, 14, { GPIODV_25 }, 1 }, 393 { "i2c_sda_b", REG1, 13, { GPIODV_26 }, 1 }, 394 { "i2c_sck_b", REG1, 12, { GPIODV_27 }, 1 }, 395 { "i2c_sda_c", REG1, 11, { GPIODV_28 }, 1 }, 396 { "i2c_sck_c", REG1, 10, { GPIODV_29 }, 1 }, 397 { "pwm_b", REG2, 11, { GPIODV_29 }, 1 }, 398 { "pwm_d", REG2, 12, { GPIODV_28 }, 1 }, 399 { "tsin_a_d0", REG2, 4, { GPIODV_0 }, 1 }, 400 { "tsin_a_dp", REG2, 3, { GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7 }, 7 }, 401 { "tsin_a_clk", REG2, 2, { GPIODV_8 }, 1 }, 402 { "tsin_a_sop", REG2, 1, { GPIODV_9 }, 1 }, 403 { "tsin_a_d_valid", REG2, 0, { GPIODV_10 }, 1 }, 404 { "tsin_a_fail", REG1, 31, { GPIODV_11 }, 1 }, 405 406 /* BOOT */ 407 { "emmc_nand_d07", REG7, 31, { BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 }, 8 }, 408 { "emmc_clk", REG7, 30, { BOOT_8 }, 1 }, 409 { "emmc_cmd", REG7, 29, { BOOT_10 }, 1 }, 410 { "emmc_ds", REG7, 28, { BOOT_15 }, 1 }, 411 { "nor_d", REG7, 13, { BOOT_11 }, 1 }, 412 { "nor_q", REG7, 12, { BOOT_12 }, 1 }, 413 { "nor_c", REG7, 11, { BOOT_13 }, 1 }, 414 { "nor_cs", REG7, 10, { BOOT_15 }, 1 }, 415 { "nand_ce0", REG7, 7, { BOOT_8 }, 1 }, 416 { "nand_ce1", REG7, 6, { BOOT_9 }, 1 }, 417 { "nand_rb0", REG7, 5, { BOOT_10 }, 1 }, 418 { "nand_ale", REG7, 4, { BOOT_11 }, 1 }, 419 { "nand_cle", REG7, 3, { BOOT_12 }, 1 }, 420 { "nand_wen_clk", REG7, 2, { BOOT_13 }, 1 }, 421 { "nand_ren_wr", REG7, 1, { BOOT_14 }, 1 }, 422 { "nand_dqs", REG7, 0, { BOOT_15 }, 1 }, 423 424 /* CARD */ 425 { "sdcard_d1", REG6, 5, { CARD_0 }, 1 }, 426 { "sdcard_d0", REG6, 4, { CARD_1 }, 1 }, 427 { "sdcard_d3", REG6, 1, { CARD_4 }, 1 }, 428 { "sdcard_d2", REG6, 0, { CARD_5 }, 1 }, 429 { "sdcard_cmd", REG6, 2, { CARD_3 }, 1 }, 430 { "sdcard_clk", REG6, 3, { CARD_2 }, 1 }, 431 432 /* GPIOCLK */ 433 { "pwm_f_clk", REG8, 30, { GPIOCLK_1 }, 1 }, 434 }; 435 436 static const struct meson_pinctrl_group mesongxl_aobus_groups[] = { 437 /* GPIOAO */ 438 { "uart_tx_ao_b_0", AOREG0, 26, { GPIOAO_0 }, 1 }, 439 { "uart_rx_ao_b_1", AOREG0, 25, { GPIOAO_1 }, 1 }, 440 { "uart_tx_ao_b", AOREG0, 24, { GPIOAO_4 }, 1 }, 441 { "uart_rx_ao_b", AOREG0, 23, { GPIOAO_5 }, 1 }, 442 { "uart_tx_ao_a", AOREG0, 12, { GPIOAO_0 }, 1 }, 443 { "uart_rx_ao_a", AOREG0, 11, { GPIOAO_1 }, 1 }, 444 { "uart_cts_ao_a", AOREG0, 10, { GPIOAO_2 }, 1 }, 445 { "uart_rts_ao_a", AOREG0, 9, { GPIOAO_3 }, 1 }, 446 { "uart_cts_ao_b", AOREG0, 8, { GPIOAO_2 }, 1 }, 447 { "uart_rts_ao_b", AOREG0, 7, { GPIOAO_3 }, 1 }, 448 { "i2c_sck_ao", AOREG0, 6, { GPIOAO_4 }, 1 }, 449 { "i2c_sda_ao", AOREG0, 5, { GPIOAO_5 }, 1 }, 450 { "i2c_slave_sck_ao", AOREG0, 2, { GPIOAO_4 }, 1 }, 451 { "i2c_slave_sda_ao", AOREG0, 1, { GPIOAO_5 }, 1 }, 452 { "remote_input_ao", AOREG0, 0, { GPIOAO_7 }, 1 }, 453 { "pwm_ao_a_3", AOREG0, 22, { GPIOAO_3 }, 1 }, 454 { "pwm_ao_b_6", AOREG0, 18, { GPIOAO_6 }, 1 }, 455 { "pwm_ao_a_8", AOREG0, 17, { GPIOAO_8 }, 1 }, 456 { "pwm_ao_b", AOREG0, 3, { GPIOAO_9 }, 1 }, 457 { "i2s_out_ch23_ao", AOREG1, 0, { GPIOAO_8 }, 1 }, 458 { "i2s_out_ch45_ao", AOREG1, 1, { GPIOAO_9 }, 1 }, 459 { "spdif_out_ao_6", AOREG0, 16, { GPIOAO_6 }, 1 }, 460 { "spdif_out_ao_9", AOREG0, 4, { GPIOAO_9 }, 1 }, 461 { "ao_cec", AOREG0, 15, { GPIOAO_8 }, 1 }, 462 { "ee_cec", AOREG0, 14, { GPIOAO_8 }, 1 }, 463 464 /* TEST_N */ 465 { "i2s_out_ch67_ao", AOREG1, 2, { GPIO_TEST_N }, 1 }, 466 467 }; 468 469 const struct meson_pinctrl_config mesongxl_periphs_pinctrl_config = { 470 .name = "Meson GXL periphs GPIO", 471 .groups = mesongxl_periphs_groups, 472 .ngroups = __arraycount(mesongxl_periphs_groups), 473 .gpios = mesongxl_periphs_gpios, 474 .ngpios = __arraycount(mesongxl_periphs_gpios), 475 }; 476 477 const struct meson_pinctrl_config mesongxl_aobus_pinctrl_config = { 478 .name = "Meson GXL AO GPIO", 479 .groups = mesongxl_aobus_groups, 480 .ngroups = __arraycount(mesongxl_aobus_groups), 481 .gpios = mesongxl_aobus_gpios, 482 .ngpios = __arraycount(mesongxl_aobus_gpios), 483 }; 484
Indexes created Wed Oct 01 19:09:53 GMT 2025