1 /* $NetBSD: nislands_smc.h,v 1.3 2021/12/18 23:45:42 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __NISLANDS_SMC_H__ 26 #define __NISLANDS_SMC_H__ 27 28 #pragma pack(push, 1) 29 30 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 31 32 struct PP_NIslands_Dpm2PerfLevel 33 { 34 uint8_t MaxPS; 35 uint8_t TgtAct; 36 uint8_t MaxPS_StepInc; 37 uint8_t MaxPS_StepDec; 38 uint8_t PSST; 39 uint8_t NearTDPDec; 40 uint8_t AboveSafeInc; 41 uint8_t BelowSafeInc; 42 uint8_t PSDeltaLimit; 43 uint8_t PSDeltaWin; 44 uint8_t Reserved[6]; 45 }; 46 47 typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel; 48 49 struct PP_NIslands_DPM2Parameters 50 { 51 uint32_t TDPLimit; 52 uint32_t NearTDPLimit; 53 uint32_t SafePowerLimit; 54 uint32_t PowerBoostLimit; 55 }; 56 typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters; 57 58 struct NISLANDS_SMC_SCLK_VALUE 59 { 60 uint32_t vCG_SPLL_FUNC_CNTL; 61 uint32_t vCG_SPLL_FUNC_CNTL_2; 62 uint32_t vCG_SPLL_FUNC_CNTL_3; 63 uint32_t vCG_SPLL_FUNC_CNTL_4; 64 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 65 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 66 uint32_t sclk_value; 67 }; 68 69 typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE; 70 71 struct NISLANDS_SMC_MCLK_VALUE 72 { 73 uint32_t vMPLL_FUNC_CNTL; 74 uint32_t vMPLL_FUNC_CNTL_1; 75 uint32_t vMPLL_FUNC_CNTL_2; 76 uint32_t vMPLL_AD_FUNC_CNTL; 77 uint32_t vMPLL_AD_FUNC_CNTL_2; 78 uint32_t vMPLL_DQ_FUNC_CNTL; 79 uint32_t vMPLL_DQ_FUNC_CNTL_2; 80 uint32_t vMCLK_PWRMGT_CNTL; 81 uint32_t vDLL_CNTL; 82 uint32_t vMPLL_SS; 83 uint32_t vMPLL_SS2; 84 uint32_t mclk_value; 85 }; 86 87 typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE; 88 89 struct NISLANDS_SMC_VOLTAGE_VALUE 90 { 91 uint16_t value; 92 uint8_t index; 93 uint8_t padding; 94 }; 95 96 typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE; 97 98 struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL 99 { 100 uint8_t arbValue; 101 uint8_t ACIndex; 102 uint8_t displayWatermark; 103 uint8_t gen2PCIE; 104 uint8_t reserved1; 105 uint8_t reserved2; 106 uint8_t strobeMode; 107 uint8_t mcFlags; 108 uint32_t aT; 109 uint32_t bSP; 110 NISLANDS_SMC_SCLK_VALUE sclk; 111 NISLANDS_SMC_MCLK_VALUE mclk; 112 NISLANDS_SMC_VOLTAGE_VALUE vddc; 113 NISLANDS_SMC_VOLTAGE_VALUE mvdd; 114 NISLANDS_SMC_VOLTAGE_VALUE vddci; 115 NISLANDS_SMC_VOLTAGE_VALUE std_vddc; 116 uint32_t powergate_en; 117 uint8_t hUp; 118 uint8_t hDown; 119 uint8_t stateFlags; 120 uint8_t arbRefreshState; 121 uint32_t SQPowerThrottle; 122 uint32_t SQPowerThrottle_2; 123 uint32_t reserved[2]; 124 PP_NIslands_Dpm2PerfLevel dpm2; 125 }; 126 127 #define NISLANDS_SMC_STROBE_RATIO 0x0F 128 #define NISLANDS_SMC_STROBE_ENABLE 0x10 129 130 #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01 131 #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02 132 #define NISLANDS_SMC_MC_RTT_ENABLE 0x04 133 #define NISLANDS_SMC_MC_STUTTER_EN 0x08 134 135 typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL; 136 137 struct NISLANDS_SMC_SWSTATE 138 { 139 uint8_t flags; 140 uint8_t levelCount; 141 uint8_t padding2; 142 uint8_t padding3; 143 NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1]; 144 }; 145 146 typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE; 147 148 #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0 149 #define NISLANDS_SMC_VOLTAGEMASK_MVDD 1 150 #define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2 151 #define NISLANDS_SMC_VOLTAGEMASK_MAX 4 152 153 struct NISLANDS_SMC_VOLTAGEMASKTABLE 154 { 155 uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 156 uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 157 }; 158 159 typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE; 160 161 #define NISLANDS_MAX_NO_VREG_STEPS 32 162 163 struct NISLANDS_SMC_STATETABLE 164 { 165 uint8_t thermalProtectType; 166 uint8_t systemFlags; 167 uint8_t maxVDDCIndexInPPTable; 168 uint8_t extraFlags; 169 uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 170 uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 171 NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; 172 PP_NIslands_DPM2Parameters dpm2Params; 173 NISLANDS_SMC_SWSTATE initialState; 174 NISLANDS_SMC_SWSTATE ACPIState; 175 NISLANDS_SMC_SWSTATE ULVState; 176 NISLANDS_SMC_SWSTATE driverState; 177 NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1]; 178 }; 179 180 typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE; 181 182 #define NI_SMC_SOFT_REGISTERS_START 0x108 183 184 #define NI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0 185 #define NI_SMC_SOFT_REGISTER_delay_bbias 0xC 186 #define NI_SMC_SOFT_REGISTER_delay_vreg 0x10 187 #define NI_SMC_SOFT_REGISTER_delay_acpi 0x2C 188 #define NI_SMC_SOFT_REGISTER_seq_index 0x64 189 #define NI_SMC_SOFT_REGISTER_mvdd_chg_time 0x68 190 #define NI_SMC_SOFT_REGISTER_mclk_switch_lim 0x78 191 #define NI_SMC_SOFT_REGISTER_watermark_threshold 0x80 192 #define NI_SMC_SOFT_REGISTER_mc_block_delay 0x84 193 #define NI_SMC_SOFT_REGISTER_uvd_enabled 0x98 194 195 #define SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES 16 196 #define SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 197 #define SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 198 #define SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES 4 199 200 struct SMC_NISLANDS_MC_TPP_CAC_TABLE 201 { 202 uint32_t tpp[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES]; 203 uint32_t cacValue[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES]; 204 }; 205 206 typedef struct SMC_NISLANDS_MC_TPP_CAC_TABLE SMC_NISLANDS_MC_TPP_CAC_TABLE; 207 208 209 struct PP_NIslands_CACTABLES 210 { 211 uint32_t cac_bif_lut[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES]; 212 uint32_t cac_lkge_lut[SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES]; 213 214 uint32_t pwr_const; 215 216 uint32_t dc_cacValue; 217 uint32_t bif_cacValue; 218 uint32_t lkge_pwr; 219 220 uint8_t cac_width; 221 uint8_t window_size_p2; 222 223 uint8_t num_drop_lsb; 224 uint8_t padding_0; 225 226 uint32_t last_power; 227 228 uint8_t AllowOvrflw; 229 uint8_t MCWrWeight; 230 uint8_t MCRdWeight; 231 uint8_t padding_1[9]; 232 233 uint8_t enableWinAvg; 234 uint8_t numWin_TDP; 235 uint8_t l2numWin_TDP; 236 uint8_t WinIndex; 237 238 uint32_t dynPwr_TDP[4]; 239 uint32_t lkgePwr_TDP[4]; 240 uint32_t power_TDP[4]; 241 uint32_t avg_dynPwr_TDP; 242 uint32_t avg_lkgePwr_TDP; 243 uint32_t avg_power_TDP; 244 uint32_t lts_power_TDP; 245 uint8_t lts_truncate_n; 246 uint8_t padding_2[7]; 247 }; 248 249 typedef struct PP_NIslands_CACTABLES PP_NIslands_CACTABLES; 250 251 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32 252 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 253 254 struct SMC_NIslands_MCRegisterAddress 255 { 256 uint16_t s0; 257 uint16_t s1; 258 }; 259 260 typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress; 261 262 263 struct SMC_NIslands_MCRegisterSet 264 { 265 uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 266 }; 267 268 typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet; 269 270 struct SMC_NIslands_MCRegisters 271 { 272 uint8_t last; 273 uint8_t reserved[3]; 274 SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 275 SMC_NIslands_MCRegisterSet data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; 276 }; 277 278 typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters; 279 280 struct SMC_NIslands_MCArbDramTimingRegisterSet 281 { 282 uint32_t mc_arb_dram_timing; 283 uint32_t mc_arb_dram_timing2; 284 uint8_t mc_arb_rfsh_rate; 285 uint8_t padding[3]; 286 }; 287 288 typedef struct SMC_NIslands_MCArbDramTimingRegisterSet SMC_NIslands_MCArbDramTimingRegisterSet; 289 290 struct SMC_NIslands_MCArbDramTimingRegisters 291 { 292 uint8_t arb_current; 293 uint8_t reserved[3]; 294 SMC_NIslands_MCArbDramTimingRegisterSet data[20]; 295 }; 296 297 typedef struct SMC_NIslands_MCArbDramTimingRegisters SMC_NIslands_MCArbDramTimingRegisters; 298 299 struct SMC_NISLANDS_SPLL_DIV_TABLE 300 { 301 uint32_t freq[256]; 302 uint32_t ss[256]; 303 }; 304 305 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff 306 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0 307 #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000 308 #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25 309 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff 310 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0 311 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000 312 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20 313 314 typedef struct SMC_NISLANDS_SPLL_DIV_TABLE SMC_NISLANDS_SPLL_DIV_TABLE; 315 316 #define NISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x100 317 318 #define NISLANDS_SMC_FIRMWARE_HEADER_version 0x0 319 #define NISLANDS_SMC_FIRMWARE_HEADER_flags 0x4 320 #define NISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0x8 321 #define NISLANDS_SMC_FIRMWARE_HEADER_stateTable 0xC 322 #define NISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x10 323 #define NISLANDS_SMC_FIRMWARE_HEADER_cacTable 0x14 324 #define NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20 325 #define NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x2C 326 #define NISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x30 327 328 #pragma pack(pop) 329 330 #endif 331 332
Indexes created Sat Sep 20 22:09:52 GMT 2025