1 /* $NetBSD: cacreg.h,v 1.12 2022/11/01 19:24:30 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Jonathan Lemon 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #ifndef _IC_CACREG_H_ 59 #define _IC_CACREG_H_ 60 61 /* Board register offsets */ 62 #define CAC_REG_CMD_FIFO 0x04 63 #define CAC_REG_DONE_FIFO 0x08 64 #define CAC_REG_INTR_MASK 0x0C 65 #define CAC_REG_STATUS 0x10 66 #define CAC_REG_INTR_PENDING 0x14 67 68 #define CAC_42REG_CMD_FIFO 0x40 69 #define CAC_42REG_DONE_FIFO 0x44 70 #define CAC_42REG_INTR_MASK 0x34 71 #define CAC_42REG_STATUS 0x30 72 73 #define CAC_42_EXTINT 0x08 74 75 #define CAC_EISAREG_INTR_MASK 0x01 76 #define CAC_EISAREG_LOCAL_MASK 0x04 77 #define CAC_EISAREG_LOCAL_DOORBELL 0x05 78 #define CAC_EISAREG_SYSTEM_MASK 0x06 79 #define CAC_EISAREG_SYSTEM_DOORBELL 0x07 80 #define CAC_EISAREG_LIST_ADDR 0x08 81 #define CAC_EISAREG_LIST_LEN 0x0c 82 #define CAC_EISAREG_TAG 0x0f 83 #define CAC_EISAREG_COMPLETE_ADDR 0x10 84 #define CAC_EISAREG_LIST_STATUS 0x16 85 86 /* EISA channel control */ 87 #define CAC_EISA_CHANNEL_BUSY 0x01 88 #define CAC_EISA_CHANNEL_CLEAR 0x02 89 90 /* Interrupt mask values */ 91 #define CAC_INTR_DISABLE 0x00 92 #define CAC_INTR_ENABLE 0x01 93 94 /* Command types */ 95 #define CAC_CMD_GET_LOG_DRV_INFO 0x10 96 #define CAC_CMD_GET_CTRL_INFO 0x11 97 #define CAC_CMD_SENSE_DRV_STATUS 0x12 98 #define CAC_CMD_START_RECOVERY 0x13 99 #define CAC_CMD_GET_PHYS_DRV_INFO 0x15 100 #define CAC_CMD_BLINK_DRV_LEDS 0x16 101 #define CAC_CMD_SENSE_DRV_LEDS 0x17 102 #define CAC_CMD_GET_LOG_DRV_EXT 0x18 103 #define CAC_CMD_GET_CTRL_INFO 0x11 104 #define CAC_CMD_READ 0x20 105 #define CAC_CMD_WRITE 0x30 106 #define CAC_CMD_WRITE_MEDIA 0x31 107 #define CAC_CMD_GET_CONFIG 0x50 108 #define CAC_CMD_SET_CONFIG 0x51 109 #define CAC_CMD_START_FIRMWARE 0x99 110 #define CAC_CMD_FLUSH_CACHE 0xc2 111 112 /* Return status codes */ 113 #define CAC_RET_SOFT_ERROR 0x02 114 #define CAC_RET_HARD_ERROR 0x04 115 #define CAC_RET_INVAL_BLOCK 0x10 116 #define CAC_RET_CMD_REJECTED 0x14 117 118 struct cac_drive_info { 119 u_int16_t secsize; 120 u_int32_t secperunit; 121 u_int16_t ncylinders; 122 u_int8_t nheads; 123 u_int8_t signature; 124 u_int8_t psectors; 125 u_int16_t wprecomp; 126 u_int8_t max_acc; 127 u_int8_t control; 128 u_int16_t pcylinders; 129 u_int8_t ptracks; 130 u_int16_t landing_zone; 131 u_int8_t nsectors; 132 u_int8_t checksum; 133 u_int8_t mirror; 134 } __packed; 135 136 struct cac_controller_info { 137 u_int8_t num_drvs; 138 u_int32_t signature; 139 u_int8_t firm_rev[4]; 140 u_int8_t rom_rev[4]; 141 u_int8_t hw_rev; 142 u_int32_t bb_rev; 143 u_int32_t drv_present_map; 144 u_int32_t ext_drv_map; 145 u_int32_t board_id; 146 u_int8_t cfg_error; 147 u_int32_t non_disk_bits; 148 u_int8_t bad_ram_addr; 149 u_int8_t cpu_rev; 150 u_int8_t pdpi_rev; 151 u_int8_t epic_rev; 152 u_int8_t wcxc_rev; 153 u_int8_t marketing_rev; 154 u_int8_t ctlr_flags; 155 u_int8_t host_flags; 156 u_int8_t expand_dis; 157 u_int8_t scsi_chips; 158 u_int32_t max_req_blocks; 159 u_int32_t ctlr_clock; 160 u_int8_t drvs_per_bus; 161 u_int16_t big_drv_present_map[8]; 162 u_int16_t big_ext_drv_map[8]; 163 u_int16_t big_non_disk_map[8]; 164 u_int16_t task_flags; 165 u_int8_t icl_bus; 166 u_int8_t red_modes; 167 u_int8_t cur_red_mode; 168 u_int8_t red_ctlr_stat; 169 u_int8_t red_fail_reason; 170 u_int8_t reserved[403]; 171 } __packed; 172 173 struct cac_drive_status { 174 u_int8_t stat; 175 #define CAC_LD_OK 0 176 #define CAC_LD_FAILED 1 177 #define CAC_LD_UNCONF 2 178 #define CAC_LD_DEGRAD 3 179 #define CAC_LD_RBLDRD 4 /* ready for rebuild */ 180 #define CAC_LD_REBLD 5 181 #define CAC_LD_PDINV 6 /* wrong phys drive replaced */ 182 #define CAC_LD_PDUNC 7 /* phys drive is not connected proper */ 183 #define CAC_LD_EXPND 10 /* expanding */ 184 #define CAC_LD_NORDY 11 /* volume is not ready */ 185 #define CAC_LD_QEXPND 12 /* queued for expansion */ 186 u_int8_t failed[4]; /* failed map */ 187 u_int8_t res0[416]; 188 u_int8_t prog[4]; /* blocks left to rebuild/expand */ 189 u_int8_t rebuild; /* drive that is rebuilding */ 190 u_int16_t remapcnt[32]; /* count of re3mapped blocks for pds */ 191 u_int8_t replaced[4]; /* replaced drives map */ 192 u_int8_t spare[4]; /* used spares map */ 193 u_int8_t sparestat; /* spare status */ 194 #define CAC_LD_CONF 0x01 /* spare configured */ 195 #define CAC_LD_RBLD 0x02 /* spare is used and rebuilding */ 196 #define CAC_LD_DONE 0x04 /* spare rebuild done */ 197 #define CAC_LD_FAIL 0x08 /* at least one spare drive has failed */ 198 #define CAC_LD_USED 0x10 /* at least one spare drive is used */ 199 #define CAC_LD_AVAIL 0x20 /* at least one spare is available */ 200 u_int8_t sparemap[32]; /* spare->pd replacement map */ 201 u_int8_t replok[4]; /* replaced failed map */ 202 u_int8_t readyok; /* ready to become ok */ 203 u_int8_t memfail; /* cache mem failure */ 204 u_int8_t expfail; /* expansion failure */ 205 u_int8_t rebldfail; /* rebuild failure */ 206 #define CAC_LD_RBLD_READ 0x01 /* read failed */ 207 #define CAC_LD_RBLD_WRITE 0x02 /* write fail */ 208 u_int8_t bigfailed[16]; /* bigmap vers of same of the above */ 209 u_int8_t bigremapcnt[256]; 210 u_int8_t bigreplaced[16]; 211 u_int8_t bigspare[16]; 212 u_int8_t bigsparemap[128]; 213 u_int8_t bigreplok[16]; 214 u_int8_t bigrebuild; /* big-number rebuilding driveno */ 215 } __packed; 216 217 struct cac_blink { 218 u_int32_t duration; /* x100ms */ 219 u_int32_t elapsed; /* only for sense */ 220 u_int8_t pdtab[256]; 221 #define CAC_BLINK_ALL 1 222 #define CAC_BLINK_TIMED 2 223 u_int8_t res[248]; 224 } __packed; 225 226 struct cac_hdr { 227 u_int8_t drive; /* logical drive */ 228 u_int8_t priority; /* block priority */ 229 u_int16_t size; /* size of request, in words */ 230 } __packed; 231 232 struct cac_req { 233 u_int16_t next; /* offset of next request */ 234 u_int8_t command; /* command */ 235 u_int8_t error; /* return error code */ 236 u_int32_t blkno; /* block number */ 237 u_int16_t bcount; /* block count */ 238 u_int8_t sgcount; /* number of scatter/gather entries */ 239 u_int8_t reserved; /* reserved */ 240 } __packed; 241 242 struct cac_sgb { 243 u_int32_t length; /* length of S/G segment */ 244 u_int32_t addr; /* physical address of block */ 245 } __packed; 246 247 #endif /* !_IC_CACREG_H_ */ 248
Indexes created Sun Sep 21 16:09:51 GMT 2025