| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 710 u32 num_heads; /* number of active crtcs */ member in struct:dce10_wm_params
903 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
904 (wm->num_heads * cursor_line_pair_return_time);
910 if (wm->num_heads == 0)
924 b.full = dfixed_const(wm->num_heads);
959 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
979 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1026 * @num_heads: number of display controllers in use
1033 u32 lb_size, u32 num_heads)
1042 if (amdgpu_crtc->base.enabled && num_heads && mode)
1166 u32 num_heads = 0, lb_size; local in function:dce_v10_0_bandwidth_update
[all...] |
| amdgpu_dce_v11_0.c | 736 u32 num_heads; /* number of active crtcs */ member in struct:dce10_wm_params
929 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
930 (wm->num_heads * cursor_line_pair_return_time);
936 if (wm->num_heads == 0)
950 b.full = dfixed_const(wm->num_heads);
985 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1005 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1052 * @num_heads: number of display controllers in use
1059 u32 lb_size, u32 num_heads)
1068 if (amdgpu_crtc->base.enabled && num_heads && mode)
1192 u32 num_heads = 0, lb_size; local in function:dce_v11_0_bandwidth_update
[all...] |
| amdgpu_dce_v6_0.c | 508 u32 num_heads; /* number of active crtcs */ member in struct:dce6_wm_params
701 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
702 (wm->num_heads * cursor_line_pair_return_time);
708 if (wm->num_heads == 0)
722 b.full = dfixed_const(wm->num_heads);
757 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads))
777 (dce_v6_0_available_bandwidth(wm) / wm->num_heads))
824 * @num_heads: number of display controllers in use
831 u32 lb_size, u32 num_heads)
845 if (amdgpu_crtc->base.enabled && num_heads && mode)
1067 u32 num_heads = 0, lb_size; local in function:dce_v6_0_bandwidth_update
[all...] |
| amdgpu_dce_v8_0.c | 645 u32 num_heads; /* number of active crtcs */ member in struct:dce8_wm_params
838 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
839 (wm->num_heads * cursor_line_pair_return_time);
845 if (wm->num_heads == 0)
859 b.full = dfixed_const(wm->num_heads);
894 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
914 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
961 * @num_heads: number of display controllers in use
968 u32 lb_size, u32 num_heads)
977 if (amdgpu_crtc->base.enabled && num_heads && mode)
1103 u32 num_heads = 0, lb_size; local in function:dce_v8_0_bandwidth_update
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_evergreen.c | 1946 u32 num_heads; /* number of active crtcs */ member in struct:evergreen_wm_params
2074 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
2075 (wm->num_heads * cursor_line_pair_return_time);
2080 if (wm->num_heads == 0)
2094 b.full = dfixed_const(wm->num_heads);
2116 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
2125 (evergreen_available_bandwidth(wm) / wm->num_heads))
2159 u32 lb_size, u32 num_heads)
2174 if (radeon_crtc->base.enabled && num_heads && mode) {
2209 wm_high.num_heads = num_heads
2330 u32 num_heads = 0, lb_size; local in function:evergreen_bandwidth_update
[all...] |
| radeon_si.c | 2074 u32 num_heads; /* number of active crtcs */ member in struct:dce6_wm_params
2219 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
2220 (wm->num_heads * cursor_line_pair_return_time);
2226 if (wm->num_heads == 0)
2240 b.full = dfixed_const(wm->num_heads);
2264 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
2273 (dce6_available_bandwidth(wm) / wm->num_heads))
2307 u32 lb_size, u32 num_heads)
2321 if (radeon_crtc->base.enabled && num_heads && mode) {
2360 wm_high.num_heads = num_heads
2475 u32 num_heads = 0, lb_size; local in function:dce6_bandwidth_update
[all...] |
| radeon_cik.c | 8991 u32 num_heads; /* number of active crtcs */ member in struct:dce8_wm_params
9184 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
9185 (wm->num_heads * cursor_line_pair_return_time);
9191 if (wm->num_heads == 0)
9205 b.full = dfixed_const(wm->num_heads);
9240 (dce8_dram_bandwidth_for_display(wm) / wm->num_heads))
9260 (dce8_available_bandwidth(wm) / wm->num_heads))
9307 * @num_heads: number of display controllers in use
9314 u32 lb_size, u32 num_heads)
9323 if (radeon_crtc->base.enabled && num_heads && mode)
9451 u32 num_heads = 0, lb_size; local in function:dce8_bandwidth_update
[all...] |
